MM912F634CV2AP datasheet(165/335 Pages) FREESCALE

165 / 335 page

Functional Description and Application Information

Port Integration Module (9S12I32PIMV1)

MM912F634

Freescale Semiconductor

165

4.27.3.1

Port A Data Register (PTA)

Table 217. Port A Data Register (PTA)

Address 0x0000

Access: User read/write(147)

543

210

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

SPI

Function

——

SCK

MOSI

MISO

Reset

000

Note:

147. Read: Anytime.

Write: Anytime.

Table 218. Port A Data Register Description

Field

Description

PTA

Port A general purpose input/output data

—Data Register

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and

synchronized pin input state is read.

PTA

Port A general purpose input/output data

—Data Register

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and

synchronized pin input state is read.

PTA

Port A general purpose input/output data

—Data Register

Port A pin 3 is associated with the SS signal of the SPI module.

When not used with the alternative function, this pin can be used as general purpose I/O.

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and

synchronized pin input state is read.

PTA

Port A general purpose input/output data

—Data Register

Port A pin 2 is associated with the SCK signal of the SPI module.

When not used with the alternative function, this pin can be used as general purpose I/O.

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and

synchronized pin input state is read.

PTA

Port A general purpose input/output data

—Data Register

Port A pin 1 is associated with the MOSI signal of the SPI module.

When not used with the alternative function, this pin can be used as general purpose I/O.

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and

synchronized pin input state is read.

PTA

Port A general purpose input/output data

—Data Register

Port A pin 0 is associated with the MISO signal of the SPI module.

When not used with the alternative function, this pin can be used as general purpose I/O.

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and

synchronized pin input state is read.

MM912F634CV2AP Datasheet(PDF) 165 Page - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 165 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL