MM912F634CV2AP datasheet(166/335 Pages) FREESCALE

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Functional Description and Application Information

Port Integration Module (9S12I32PIMV1)

MM912F634

Freescale Semiconductor

166

4.27.3.2

PIM Reserved Register

4.27.3.3

Port A Data Direction Register (DDRA)

4.27.3.4

PIM Reserved Register

Table 219. PIM Reserved Register

Address 0x0001

Access: User read(148)

543

210

Reset

000

Note:

148. Read: Anytime.

Write: Unimplemented. Writing to this register has no effect.

Table 220. Port A Data Direction Register (DDRA)

Address 0x0002

Access: User read/write(149)

543

210

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Reset

000

Note:

149. Read: Anytime.

Write: Anytime.

Table 221. DDRA Register Field Descriptions

Field

Description

5-0

DDRA

Port A Data Direction

—

This register controls the data direction of pins 5 through 0.

The SPI function controls the data direction for the associated pins. In this case the data direction bits will not change.

When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output.

1 Associated pin is configured as output.

0 Associated pin is configured as high-impedance input.

Table 222. PIM Reserved Register

Address 0x0003

Access: User read(150)

543

210

Reset

000

Note:

150. Read: Anytime.

Write: Unimplemented. Writing to this register has no effect.

MM912F634CV2AP Datasheet(PDF) 166 Page - Freescale Semiconductor, Inc

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