MM912F634CV2AP datasheet(156/335 Pages) FREESCALE

156 / 335 page

Functional Description and Application Information

MM912F634 - MCU Die Overview

MM912F634

Freescale Semiconductor

156

4.26.1.2

Modes of Operation

Memory map and bus interface modes:

•

Normal operating mode

— Normal single-chip mode

•

Special Operating mode

— Special single-chip mode with active background debug mode

Low-power modes:

•

System stop mode

•

System wait mode

4.26.2

Block Diagrams

Figure 43 shows a block diagram of the MC9S12I32device

Figure 43. MC9S12I32 Block Diagram

4.26.3

Device Memory Map

4.26.3.1

Address Mapping

Figure 44 shows S12S CPU & BDM local address translation to the global memory map. It also indicates the location of the

internal resources in the memory map.

2K bytes RAM

RESET

EXTAL

XTAL

BKGD

Real Time Interrupt

Osc Clock Monitor

Single-wire Background

TEST

Debug Module

Interrupt Module

32K bytes Flash

CPU12

COP Watchdog

Debug Module

2 address breakpoints

64 Byte Trace Buffer

Reset Generation

and Test Entry

Die-to-Die

PD3

PD0

PD1

PD2

D2D[0]

D2D[1]

PD7

PD4

PD5

PD6

PA3

PA0

PA1

PA2

PA4

PA5

VDDX

VSSX

Initiator

scalable 4 or 8 bits wide

D2D[2]

D2D[3]

D2D[4]

D2D[5]

D2D[6]

D2D[7]

VDD

VSS

SPI

MISO

MOSI

SCK

PC0

PC1

D2DCLK

D2DINT

Full Swing Pierce

Oscillator

Internal Reference Clock

MM912F634CV2AP Datasheet(PDF) 156 Page - Freescale Semiconductor, Inc

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