MM912F634CV2AP datasheet(152/335 Pages) FREESCALE

152 / 335 page

Functional Description and Application Information

MM912F634 - Analog Die Trimming

MM912F634

Freescale Semiconductor

152

4.25.1.2

4.25.1.2.1

Trimming Register 0 (CTR0)

4.25.1.2.2

Trimming Register 1 (CTR1)

Table 204. Trimming Register 0 (CTR0)

Offset(137) 0xF0

Access: User read/write

543

LINTRE

LINTR

WDCTRE

CTR0_4

CTR0_3

WDCTR2

WDCTR1

WDCTR0

Reset

000

Note:

137. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 205. CTR0 - Register Field Descriptions

Field

Description

LINTRE

LIN trim enable

0 - no trim can be done

1- trim can be done by setting LINTR bit

LINTR

LIN trim bit

0 - default slope

1 - adjust the slope

WDCTRE

Watchdog trim enable

0 - no trim can be done

1 - trim can be done by setting WDCTR[2:0] bits

CTR0_4

Spare Trim bit 4

CTR0_3

Spare Trim bit 3

2-0

WDCTR2…0

Watchdog clock trim (Trim effect to the 100 kHz Watch dog base clock)

000: 0%

001: +5%

010: +10%

011: +15%

100: -20%

101: -15%

110: -10%

111: -5%

Table 206. Trimming Register 1 (CTR1)

Offset(138) 0xF1

Access: User read/write

654

321

BGTRE

CTR1_6

BGTRIMUP

BGTRIMDN

IREFTRE

IREFTR2

IREFTR1

IREFTR0

Reset

000

Note:

138. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 152 Page - Freescale Semiconductor, Inc

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