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MM912F634CV2AP Datasheet(PDF) 155 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 155 Page - Freescale Semiconductor, Inc |
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155 / 335 page  Functional Description and Application Information MM912F634 - MCU Die Overview MM912F634 Freescale Semiconductor 155 4.26 MM912F634 - MCU Die Overview 4.26.1 Introduction The MC9S12I32 micro controller implemented in the MM912F634 is the first member of the newly introduced S12S platform, mainly targeted for Intelligent Distributed Control (IDC) applications. The MC9S12I32 device is designed as counter part to an analog die, and is not being offered as a standalone MCU. The MC9S12I32 die contains a HCS12 Central Processing Unit (CPU), offering 32 kB of Flash memory and 2.0 kB of system SRAM, up to six general purpose I/Os, an on-chip oscillator and clock multiplier, one Serial Peripheral Interface (SPI), an interrupt module, and debug capabilities via the on-chip debug module (DBG) in combination with the Background Debug Mode (BDM) interface. The MC9S12I32 die has no external bus interface, and thus no emulation capability as well as no internal voltage regulator. Additionally there is a die-to-die initiator (D2DI) which represents the communication interface to the companion (analog) die. 4.26.1.1 Features • 16-Bit S12S CPU — Upward compatible with the CPU12 instruction set • Note: Five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) are not supported on this device. • INT (interrupt module) — Supporting nested interrupts • MMC (memory mapping control and crossbar switch) • DBG (debug module) — Monitoring of the CPU bus with tag-type or force-type breakpoint requests — 64 x 20-bit circular trace buffer captures change-of-flow or memory access information • BDM (background debug mode) • OSC (oscillator) — Full-swing Pierce oscillator option utilizing a 4.0 MHz to 16 MHz crystal or resonator • CRG (clock and reset generation) — 32 kHz trimmable internal reference clock — Oscillator clock monitor — Internal Digital Controlled Oscillator (DCO), Frequency Locked Loop (FLL) based • COP module (Computer Operating Properly watchdog) • RTI module (Real Time Interrupt) • Memory Options — 32 k byte Flash — 2.0 k byte RAM • Flash General Features — Erase sector size 512 bytes — Automated program and erase algorithm • Serial Peripheral Interface Module (SPI) — Configurable for 8 or 16-bit data size • Input/Output — Up to 6 general-purpose input/output (I/O) pins — Hysteresis on all input pins — Configurable drive strength on all output pins • Die 2 Die Initiator (D2DI) — Up to 2.0 Mbyte/s data rate — Configurable 4-bit or 8-bit wide data path • 20 MHz maximum CPU bus frequency (16 MHz for MM912F634CV2AP) ANALOG MCU |
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