MM912F634CV2AP datasheet(151/335 Pages) FREESCALE

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Functional Description and Application Information

MM912F634 - Analog Die Trimming

MM912F634

Freescale Semiconductor

151

4.25

MM912F634 - Analog Die Trimming

A trimming option is implemented to increase some device parameter accuracy. As the MM912F634 analog die is exclusively

combined with a FLASH- MCU, the required trimming values can be calculated during the final test of the device, and stored to

a fixed position in the FLASH memory. During start-up of the system, the trimming values have to be copied into the MM912F634

analog die trimming registers.

The trimming registers will maintain their content during Low Power mode, Reset will set the default value.

4.25.1

Memory Map and Register Definition

4.25.1.1

Module Memory Map

NOTE

Two word (16-Bit) transfers including CTR2 are recommended at system startup. The IFR

(MMCCTL1)")

To trim the bg1p25sleep there is two steps:

Step 1: First choose the right trim step by adjusting SLPBGTR[2:0] with SLPBGTRE=1,

SLPBG_LOCK bit has to stay at 0.

Step 2: Once the trim value is known, correct SLPBGTR[2:0], SLPBGTRE and

SLPBG_LOCK bits have to be set at the same time to apply and lock the trim. Once the trim

is locked, no other trim on the parameter is possible.

There are four trimming registers implemented (CTR0…CTR3), with CTR2 being reserved for future use. The following table

shows the registers used.

At system startup, the trimming information have to be copied from the MCU IFR Flash location to the corresponding MM912F634

analog die trimming registers. The following table shows the register correlation.

Table 202. MM912F634 Analog Die Trimming Registers

Offset(135)

Name

0xF0

CTR0

LINTRE

LINTR

WDCTRE

CTR0_4

CTR0_3

WDCTR2

WDCTR1

WDCTR0

Trimming Reg 0

0xF1

CTR1

BGTRE

CTR1_6

BGTRIMUP

BGTRIMDN

IREFTRE

IREFTR2

IREFTR1

IREFTR0

Trimming Reg 1

0xF2

CTR2

SLPBGTRE

SLPBG_LOCK

SLPBGTR2

SLPBGTR1

SLPBGTR0

Trimming Reg 2

0xF3

CTR3

OFFCTRE

OFFCTR2

OFFCTR1

OFFCTR0

CTR3_E

CTR3_2

CTR3_1

CTR3_0

Trimming Reg 3

Note:

135. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 203. MM912F634 - MCU vs. Analog Die Trimming Register Correlation

Name

MCU IFR Address

Analog Offset(136)

CTR0

0x4C

0xF0

CTR1

0x4D

0xF1

CTR2

0x4E

0xF2

CTR3

0x4F

0xF3

Note:

136. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 151 Page - Freescale Semiconductor, Inc

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