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MM912F634CV2AP Datasheet(PDF) 153 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 153 Page - Freescale Semiconductor, Inc |
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153 / 335 page ![]() Functional Description and Application Information MM912F634 - Analog Die Trimming MM912F634 Freescale Semiconductor 153 4.25.1.2.3 Trimming Register 2 (CTR2) Table 207. CTR1 - Register Field Descriptions Field Description 7 BGTRE Bandgap trim enable 0 - no trim can be done 1 - trim can be done by setting BGTRIMUP and BGTRIMDN bits 6 CTR1_6 Spare Trim Bit 5 BGTRIMUP Bandgap trim up bit 0 - default slope 1 - increase bandgap slope 4 BGTRIMDN Bandgap trim down bit 0 - default slope 1 - decrease bandgap slope 3 IREFTRE Iref trim enable bit 0 - no trim can be done 1 - trim can be done by setting IREFTR[2:0] bits 2-0 IREFTR2…0 Iref trim - This trim is used to adjust the internal zero TC current reference 000: 0% 001: +7.6% 010: +16.43% 011: +26.83% 100: -8.54% 101: -15.75% 110: -21.79% 111: 0% Table 208. Trimming Register 2 (CTR2) Offset(139) 0xF2 Access: User read/write 765 4 3 2 1 0 R0 0 0 SLPBGTRE SLPBG_LOCK SLPBGTR2 SLPBGTR1 SLPBGTR0 W Reset 0 0 0 0 0 000 Note: 139. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 209. CTR2 - Register Field Descriptions Field Description 4 SLPBGTRE Sleep Bandgap trim enable 0 no trim can be done 1 trim lock can be done by setting SLPBGTR[2:0] bits and SLPBG_LOCK bit 3 SLPBG_LOCK bg1p25sleep trim lock bit |
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