MM912F634CV2AP datasheet(187/335 Pages) FREESCALE

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Functional Description and Application Information

Interrupt Module (S12SINTV1)

MM912F634

Freescale Semiconductor

187

4.29

Interrupt Module (S12SINTV1)

4.29.1

Introduction

The 9S12I32PIMV1 module decodes the priority of all system exception requests and provides the applicable vector for

processing the exception to the CPU. The 9S12I32PIMV1 module supports:

•

I bit and X bit maskable interrupt requests

•

A non-maskable unimplemented opcode trap

•

A non-maskable software interrupt (SWI) or background debug mode request

•

Three system reset vector requests

•

A spurious interrupt vector

Each of the I bit maskable interrupt requests is assigned to a fixed priority level.

4.29.1.1

Glossary

CCR — Condition Code Register (in the CPU)

ISR — Interrupt Service Routine

MCU — Micro-controller Unit

4.29.1.2

Features

•

Interrupt vector base register (IVBR)

•

One spurious interrupt vector (at address vector base + 0x0080). The vector base is a 16-bit address which is

accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower

byte).

•

2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).

•

I bit maskable interrupts can be nested.

•

One X bit maskable interrupt vector request (at address vector base + 0x00F4).

•

One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base

+ 0x00F6).

•

One non-maskable unimplemented opcode trap (TRAP) vector (at address vector base + 0x00F8).

•

Three system reset vectors (at addresses 0xFFFA–0xFFFE).

•

Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU request

•

Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.

4.29.1.3

Modes of Operation

•Run mode

This is the basic mode of operation.

•

Wait mode

In wait mode, the clock to the 9S12I32PIMV1 module is disabled. The 9S12I32PIMV1 module is however capable of

waking up the CPU from wait mode if an interrupt occurs. Please refer to Section 4.29.5.3, “Wake-up from Stop or Wait

Mode"” for details.

•

Stop mode

In stop mode, the clock to the 9S12I32PIMV1 module is disabled. The 9S12I32PIMV1 module is however capable of

waking up the CPU from stop mode if an interrupt occurs. Please refer to Section 4.29.5.3, “Wake-up from Stop or Wait

Mode"” for details.

•

Freeze mode (BDM active)

In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to

Section 4.29.3.1.1, “Interrupt Vector Base Register (IVBR)"” for details.

MM912F634CV2AP Datasheet(PDF) 187 Page - Freescale Semiconductor, Inc

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