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MM912F634CV2AP Datasheet(PDF) 185 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 185 Page - Freescale Semiconductor, Inc |
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185 / 335 page  Functional Description and Application Information Memory Mapping Control (S12SMMCV1) MM912F634 Freescale Semiconductor 185 4.28.3.3 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12S masters (CPU, BDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal resources are connected to specific target buses (see Figure 56). Figure 56. S12S Platform 4.28.3.3.1 Master Bus Prioritization Regarding Access Conflicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing accesses from different masters to the same target bus: • CPU always has priority over BDM. • BDM has priority over CPU when its access is stalled for more than 128 cycles. In the later case the CPU will be stalled after finishing the current operation and the BDM will gain access to the bus. 4.28.3.4 Interrupts The MMC does not generate any interrupts CPU BDM MMC “Crossbar Switch” S12X0 XBUS0 DBG S12X1 IPBI SRAM BDM resources Peripherals FLASH |
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