BQ76PL455APFCT datasheet(102/125 Pages) TI1

102 / 125 page

102

bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

www.ti.com

Product Folder Links: bq76PL455A

Submit Documentation Feedback

Application Information (continued)

8.1.2.2.7

Isolation Capacitor

The differential signal lines are isolated between ICs by a DC blocking capacitor. The capacitor must be rated

with a high enough voltage to provide standoff margin in the event of a fault in the system that exposes the

device to a local hazardous voltage. Selecting a capacitor rated at a minimum of 2 times the stack the voltage is

the recommended practice. One capacitor is sufficient for the normal operation of the device. However, two

capacitors are used (one at each end of the cable or PCB wiring) for an additional safety factor. In these

applications, the capacitor must be doubled from the typical requirement to maintain the required capacitance in

the signal path. Connect a minimum of 1 nF, with ±10% or better tolerance and the appropriate voltage rating for

the application. In noisy environments, 2 nF is recommended.

8.1.2.2.8

Unused Differential Communications Pins

Unused stack communications pins (COMMH+/–, COMML+/–, FAULTH+/–, FAULTL+/–) have internal

terminations; no external pull-up or pull-down resistors are required on these pins, if not used. If not used, leave

the unused pins unconnected. The COMMH drivers cannot be disabled.

8.1.3 ADC

8.1.3.1 Idle (Parking) Channel Errors

Between acquisition cycles, the multiplexer idles on the highest VSENSE channel enabled for conversion by the

CHANNELS register for sampling first on the next cycle.

Parking introduces a very small error to the idle channel due to the input impedance of the device causing a

small IR drop through the external resistor, which is part of the LP filter. The error is increased when using

VSENSE series resistors greater than 100

Ω. Setting the AFE_CTL bit = 1 in this application provides the

greatest error improvement. When AFE_PCTL is set, every time cell voltage sampling requests occur, cell

voltage sampling delays by 100 µs, regardless of the power status of the AFE. This maintains sampling

synchronization between multiple chips. Changes to this bit do not take effect until after the next AFE sample

occurs.

8.1.3.2 VSENSE Channel Post-Assembly Calibration Adjustment

Use of post-assembly calibration adjustment can improve device accuracy further after exposure to soldering

and/or bake cycles in the manufacturing process. ADC gain and offset-correction factors are programmable in

the bq76PL455A to allow for post-assembly calibration. The total range of adjustment limitation for both factors is

from –9.77 mV to 9.69 mV.

Application of these gain and offset corrections is global to all VSENSE channels. The AUX channels do not

receive these corrections. Application of the corrections is to the raw ADC values after application of the factory-

stored offset and gain corrections.

Perform the correction procedures at room temperature (RT) using a stable, high-accuracy DC source and / or

voltmeter. The registers contain signed 2's complement values. A zero value in either register indicates no

correction. Measurement of two voltage points, VIN1 and VIN2, occurs for each correction. The expected

minimum and maximum values for the cell can be used; however, ensure the lowest VINMIN value is greater than

or equal to 2.0 V and the highest VINMAXis less than or equal to 4.5 V.

For best results in most designs, both VIN1 and VIN2 use the average voltage measured by each channel

VSENSE1–16 after correcting for any errors in the stimulus (source) voltages at each input.

8.1.3.2.1

Gain Error Correction

Gain Error Correction: –9.77 mV to 9.69 mV in 255 steps (8 bits) in register VSGAIN

Procedure:

1. Apply voltage VIN1, read back from ADC VOUT1, and record both.

2. Apply voltage VIN2, read back from ADC VOUT2, and record both.

3. Calculate slope m = (VOUT2–VOUT1) / (VIN2–VIN1).

4. Find the gain error correction (GEC) at 5 V in 16-bit LSB (5 V is used regardless of VINx value).

BQ76PL455APFCT Datasheet(PDF) 102 Page - Texas Instruments

BQ76PL455APFCT Datasheet(HTML) 102 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL