MM912F634CV2AP datasheet(132/335 Pages) FREESCALE

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Functional Description and Application Information

Basic Timer Module - TIM (TIM16B4C)

MM912F634

Freescale Semiconductor

132

4.18.3.3.10

Timer Interrupt Enable Register (TIE)

4.18.3.3.11

Timer System Control Register 2 (TSCR2)

NOTE

This mode of operation is similar to an up-counting modulus counter.

If register TC3 = $0000 and TCRE = 1, the timer counter register (TCNT) will stay at $0000

continuously. If register TC3 = $FFFF and TCRE = 1, TOF will not be set when the timer

counter register (TCNT) is reset from $FFFF to $0000.

The newly selected prescale factor will not take effect until the next synchronized edge,

where all prescale counter stages equal zero.

Table 171. Edge Detector Circuit Configuration

EDGnB

EDGnA

Configuration

Capture disabled

Capture on rising edges only

Capture on falling edges only

Capture on any edge (rising or falling)

Table 172. Timer Interrupt Enable Register (TIE)

Offset(117) 0xCA

Access: User read/write

543

210

000

C3I

C2I

C1I

C0I

Reset

000

Note:

117. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 173. TIE - Register Field Descriptions

Field

Description

3-0

C[3-0]I

Input Capture/Output Compare Interrupt Enable.

1 = Enables corresponding Interrupt flag (CnF of TFLG1 register) to cause a hardware interrupt

0 = Disables corresponding Interrupt flag (CnF of TFLG1 register) from causing a hardware interrupt

Table 174. Timer System Control Register 2 (TSCR2)

Offset(118) 0xCB

Access: User read/write

543

210

TOI

000

TCRE

PR2

PR1

PR0

Reset

000

Note:

118. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 175. TIE - Register Field Descriptions

Field

Description

TOI

Timer Overflow Interrupt Enable

1 = Hardware interrupt requested when TOF flag set in TFLG2 register.

0 = Hardware Interrupt request inhibited.

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