MM912F634CV2AP datasheet(134/335 Pages) FREESCALE

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Functional Description and Application Information

Basic Timer Module - TIM (TIM16B4C)

MM912F634

Freescale Semiconductor

134

4.18.3.3.13

Main Timer Interrupt Flag 2 (TFLG2)

NOTE

The TFLG2 register indicates when an interrupt has occurred. Writing a one to the TOF bit

will clear it. Any access to TCNT will clear TOF bit of TFLG2 register if the TFFCA bit in

TSCR register is set.

4.18.3.3.14

Timer Input Capture/Output Compare Registers (TC3 - TC0)

NOTE

TRead anytime. Write anytime for output compare function. Writes to these registers have

no effect during input capture.

Depending on the TIOS bit for the corresponding channel, these registers are used to latch

the value of the free-running counter when a defined transition is sensed by the

corresponding input capture edge detector or to trigger an output action for output compare.

Read/Write access in byte mode for high byte should takes place before low byte otherwise

it will give a different result.

Table 179. Main Timer Interrupt Flag 2 (TFLG2)

Offset(120) 0xCD

Access: User read/write

543

210

TOF

000

Reset

000

Note:

120. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 180. TFLG2 - Register Field Descriptions

Field

Description

TOF

Timer Overflow Flag

1 = Indicates that an Interrupt has occurred (Set when 16-bit free-running timer counter overflows from $FFFF to $0000)

0 = Flag indicates an Interrupt has not occurred.

Table 181. Timer Input Capture/Output Compare Register 0 (TC0)

Offset(121) 0xCE, 0xCF

Access: User read(anytime)/write (special mode)

tc0_15

tc0_14

tc0_13

tc0_12

tc0_11

tc0_10

tc0_9

tc0_8

Reset

000

543

210

tc0_7

tc0_6

tc0_5

tc0_4

tc0_3

tc0_2

tc0_1

tc0_0

Reset

000

Note:

121. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

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