MM912F634CV2AP datasheet(137/335 Pages) FREESCALE

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Functional Description and Application Information

Basic Timer Module - TIM (TIM16B4C)

MM912F634

Freescale Semiconductor

137

4.18.4.3

Input Capture

Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The input capture function

captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the

timer transfers the value in the timer counter into the timer channel registers, TCn.

The minimum pulse width for the input capture input is greater than two bus clocks.

An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.

4.18.4.4

Output Compare

Setting the I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate

a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel

registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets

the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.

The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both OMn and OLn

disconnects the pin from the output logic.

Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output compare does not set the

channel flag.

A successful output compare on channel 3 overrides output compares on all other output compare channels. The output compare

3 mask register masks the bits in the output compare 3 data register. The timer counter reset enable bit, TCRE, enables channel

3 output compares to reset the timer counter. A channel 3 output compare can reset the timer counter even if the IOC3 pin is

being used as the pulse accumulator input.

Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch.

When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.

4.18.5

Resets

4.18.5.1

General

The reset state of each individual bit is listed within the Register Description section 4.18.3, “Memory Map and Registers“, which

details the registers and their bit-fields.

4.18.6

Interrupts

4.18.6.1

General

This section describes interrupts originated by the TIM16B4C block. Table 186 lists the interrupts generated by the TIM16B4C to

communicate with the MCU.

Table 186. TIM16B4C Interrupts

Interrupt

Offset

Vector

Priority

Source

Description

C[3:0]F

Timer Channel 3-0

Active high timer channel interrupts 3-0

TOF

Timer Overflow

Timer Overflow interrupt

MM912F634CV2AP Datasheet(PDF) 137 Page - Freescale Semiconductor, Inc

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