MM912F634CV2AP datasheet(129/335 Pages) FREESCALE

129 / 335 page

Functional Description and Application Information

Basic Timer Module - TIM (TIM16B4C)

MM912F634

Freescale Semiconductor

129

4.18.3.3.5

Timer Count Register (TCNT)

NOTE

The 16-bit main timer is an up counter. A full access for the counter register should take

place in one clock cycle. A separate read/write for high byte and low byte will give a different

result than accessing them as a word. The period of the first count after a write to the TCNT

registers may be a different length because the write is not synchronized with the prescaler

clock.

4.18.3.3.6

Timer System Control Register 1 (TSCR1)

Table 159. OC3D - Register Field Descriptions

Field

Description

3-0

OC3D[3-0]

Output Compare 3 Data for Channel “n”

Table 160. Timer Count Register (TCNT)

Offset(112) 0xC4, 0xC5

Access: User read(anytime)/write (special mode)

tcnt15

tcnt14

tcnt13

tcnt12

tcnt11

tcnt10

tcnt9

tcnt8

Reset

000

543

210

tcnt7

tcnt6

tcnt5

tcnt4

tcnt3

tcnt2

tcnt1

tcnt0

Reset

000

Note:

112. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 161. TCNT - Register Field Descriptions

Field

Description

15-0

tcnt[15-0]

16 Bit Timer Count Register

Table 162. Timer System Control Register 1 (TSCR1)

Offset(113) 0xC6

Access: User read/write

543

210

TEN

TFFCA

Reset

000

Note:

113. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 129 Page - Freescale Semiconductor, Inc

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