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MM912F634CV2AP Datasheet(PDF) 142 Page - Freescale Semiconductor, Inc

Part # MM912F634CV2AP
Description  Integrated S12 Based Relay Driver with LIN
PDF  335 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 142 Page - Freescale Semiconductor, Inc

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Functional Description and Application Information
Analog Digital Converter - ADC
MM912F634
Freescale Semiconductor
142
4.19.4.2
Register Definition
4.19.4.2.1
ADC Config Register (ACR)
NOTE
ADCRST is strongly recommended to be set during D2D clock frequency changes.
0xA2
ADR14 (hi)
R
ADR14[9:2]
W
0xA3
ADR14 (lo)
R
ADR14[1:0]
W
0xA4
ADR15 (hi)
R
ADR15[9:2]
W
0xA5
ADR15 (lo)
R
ADR15[1:0]
W
Note:
125. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 189. ADC Config Register (ACR)
Offset(126) 0x80
Access: User read/write
76
543
210
R
SCIE
CCE
OCE
ADCRST
0
PS2
PS1
PS0
W
Reset
0
000
00
00
Note:
126. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 190. ACR - Register Field Descriptions
Field
Description
7 - SCIE
Sequence Complete Interrupt Enable
0 - Sequence Complete Interrupt Disabled
1 - Sequence Complete Interrupt Enabled
6 - CCE
Continuous Conversion Enable
0 - Continuous Conversion Disabled
1 - Continuous Conversion Enabled
5 - OCE
Offset Compensation Enable
0 - Offset Compensation Disabled
1 - Offset Compensation Enabled, This feature requires the CH15 bit in the ADC Conversion Control Register (ACCR) to
be set for all conversions.
Table 188. Analog Digital Converter Module - Memory Map (continued)
Register /
Offset(125)
Bit 7
6
5
4
3
2
1
Bit 0



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