 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MM912F634CV2AP Datasheet(PDF) 144 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MM912F634CV2AP Datasheet(HTML) 144 Page - Freescale Semiconductor, Inc |
|
|
144 / 335 page  Functional Description and Application Information Analog Digital Converter - ADC MM912F634 Freescale Semiconductor 144 4.19.4.2.4 ADC Conversion Complete Status Register (ACCSR) 4.19.4.2.5 ADC Data Result Register x (ADRx) Table 194. ACCR - Register Field Descriptions Field Description 15-0 CHx Channel Select - If 1, the selected channel is included into the sequence. Writing ACCR will stop the current sequence and restart. Writing ACCR=0 will stop the conversion, All CCx flags will be cleared when ACCR is written.Conversion will start after write. 16-Bit write operation recommended, writing 8-bit: Only writing the High Byte will start the conversion with Channel 15, if selected. Write to the Low Byte will not start a conversion. Measure individual Channels by writing a sequence of one channel. Channel 15 needs to be selected in order to have the offset compensation functional. Table 195. ADC Conversion Complete Status Register (ACCSR) Offset(129) 0x84 (0x84 and 0x85 for 8-Bit access) Access: User read 15 14 13 12 11 10 98765 43210 R CC15 CC14 0 CC12 CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 W Reset 0000000 0000000 00 Note: 129. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 196. ACCSR - Register Field Descriptions Field Description 15-0 CCx Conversion Complete Flag - Indicates the conversion being complete for channel x. Read operation only.16-bit read recommended. 8-Bit read will return the current status, no latching will be performed. Table 197. ADC Data Result Register x (ADRx) Offset(130) 0x86+x (0x86 and 0x87 for 8-Bit access) Access: User read 15 14 13 12 11 10 98765 43210 R ADRx 0 0 00 00 W Reset 0000000 0000000 00 Note: 130. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 198. ADRx - Register Field Descriptions Field Description 15-6 ADRx ADC - Channel X left adjusted Result Register. Reading the register will clear the corresponding CCx register in the ACCSR register. 16-bit read recommended. 8-Bit read: Reading the low byte will latch the high byte for the next read, reading the high byte will clear the cc flag. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
