MM912F634CV2AP datasheet(145/335 Pages) FREESCALE

145 / 335 page

Functional Description and Application Information

Analog Digital Converter - ADC

MM912F634

Freescale Semiconductor

145

4.19.5

Functional Description

4.19.5.1

Analog Channel Definitions

The following analog Channels a routed to the analog multiplexer:

(continued)

4.19.5.2

Automatic Offset Compensation

To eliminate the Analog Digital Converter Offset, an automatic compensation is implemented. The compensation is based on a

calibrated voltage reference connected to ADC Channel 15. The reference trim is accomplished by the correct CTRx Register

content. See Section 4.25, “MM912F634 - Analog Die Trimming". The reference is factory trimmed to 8 LSB.

To activate the Offset compensation feature, the OCE bit in the ADC Config Register (ACR) has to be set, and the CH15 has to

be enabled when starting a new conversion, by writing to the ADC Conversion Control Register (ACCR). The compensation will

work with single and sequence conversion.

Table 199. Analog Channels

Channel

Description

AD0 - PTB0 Analog Input

AD0

AD1 - PTB1 Analog Input

AD1

AD2 - PTB2 Analog Input

AD2

AD3 - L0 Analog Input

AD3

AD4 - L1 Analog Input

AD4

AD5 - L2 Analog Input

AD5

AD6 - L3 Analog Input

AD6

AD7 - L4 Analog Input

AD7

AD8 - L5 Analog Input

AD8

Current Sense

ISENSE

Voltage Sense

VSENSE

Temperature Sense

TSENSE

VS1 Sense

VS1SENSE

not implemented

n.i.

Bandgap(131)

BANDGAP

Calibration Reference

CAL

Note:

131. Internal “bg1p25sleep” reference.

MM912F634CV2AP Datasheet(PDF) 145 Page - Freescale Semiconductor, Inc

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