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MM912F634CV2AP Datasheet(PDF) 172 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 172 Page - Freescale Semiconductor, Inc |
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172 / 335 page ![]() Functional Description and Application Information Port Integration Module (9S12I32PIMV1) MM912F634 Freescale Semiconductor 172 4.27.4.3 Ports 4.27.4.3.1 Port A This port is associated with the SPI. Port A pins PA5-0 can be used for general-purpose I/O and PA3-0, also with the SPI subsystem. 4.27.4.3.2 Port C This port is associated with the D2DI interface. Port C pins PC1-0 can be used either for general-purpose I/O, or as the D2DI interrupt input and D2DI clock output, respectively. A pull-down device is enabled on pin PC1 if used as D2DI input. The D2DI interrupt input is synchronized and has an asynchronous bypass in STOP mode to allow the generation of a wake-up interrupt. 4.27.4.3.3 Port D This port is exclusively associated with the D2DI interface and not available externally. Port D pins PD7-0 can be used either for general-purpose I/O or with the D2DI data I/O. If the D2DI is enabled in 4-bit mode, pins PD7-4 can be used with general purpose pin functionality. Pull-down devices are enabled on all pins if used as D2DI inputs. 4.27.5 Initialization Information 4.27.5.1 Port Data and Data Direction Register writes It is not recommended to write PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. |
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