MM912F634CV2AP datasheet(175/335 Pages) FREESCALE

175 / 335 page

Functional Description and Application Information

Memory Mapping Control (S12SMMCV1)

MM912F634

Freescale Semiconductor

175

The user is advised to refer to the SoC Guide for port configuration and location of external bus signals. Some pins may not be

bonded out in all implementations.

Table 239 outlines the pin names and functions. It also provides a brief description of their operation.

4.28.2

Memory Map and Registers

4.28.2.1

Module Memory Map

A summary of the registers associated with the MMC block is shown in Figure 48. Detailed descriptions of the registers and bits

are given in the subsections that follow.

4.28.2.2

4.28.2.2.1

Program Page Index Register (PPAGE)

NOTE

Writes to this register using the special access of the CALL and RTC instructions will be

complete before the end of the instruction execution.

Read: Anytime

Write: Anytime

These four index bits are used to page 16 kByte blocks into the Flash page window located in the local (CPU or BDM) memory

map from address 0x8000 to address 0xBFFF (see Figure 49). This supports accessing up to 256 Kilobytes of Flash (in the

Table 239. External Input Signals Associated with the MMC

Signal

I/O

Description

Availability

MODC

Mode input

Latched after

RESET (active low)

Figure 48. MMC Register Summary

Address

Name

Bit 7

Bit 0

0x0030

PPAGE

PIX3

PIX2

PIX1

PIX0

0x0031

DIRECT

DP15

DP14

DP13

DP12

DP11

DP10

DP9

DP8

0x0032

MODE

MODC

000

0x0033

MMCCTL1

000

IFRON

Table 240. Program Page Index Register (PPAGE)

Address: 0x0030

432

PIX3

PIX2

PIX1

PIX0

Reset

111

MM912F634CV2AP Datasheet(PDF) 175 Page - Freescale Semiconductor, Inc

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