MM912F634CV2AP datasheet(174/335 Pages) FREESCALE

174 / 335 page

Functional Description and Application Information

Memory Mapping Control (S12SMMCV1)

MM912F634

Freescale Semiconductor

174

4.28.1.3

S12S Memory Mapping

The S12S architecture implements one memory mapping scheme including

•

A (CPU or BDM) 64 kByte local map, defined using specific resource page (PPAGE) register and the default instruction

set. The 64 Kilobytes visible at any instant can be considered as the local map accessed by the 16-bit (CPU or BDM)

address.

4.28.1.4

Modes of Operation

This subsection lists and briefly describes all operating modes supported by the MMC.

4.28.1.4.1

Power Saving Modes

•Run mode

MMC is functional during normal run mode.

•

Wait mode

MMC is functional during wait mode.

•

Stop mode

MMC is inactive during stop mode.

4.28.1.4.2

Functional Modes

•

Single chip modes

In normal and special single chip mode the internal memory is used.

4.28.1.5

Block Diagram

Figure 47 shows a block diagram of the MMC.

Figure 47. MMC Block Diagram External Signal Description

CPU

BDM

Target Bus Controller

DBG

MMC

Address Decoder & Priority

Peripherals

FLASH

RAM

MM912F634CV2AP Datasheet(PDF) 174 Page - Freescale Semiconductor, Inc

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