MM912F634CV2AP datasheet(173/335 Pages) FREESCALE

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Functional Description and Application Information

Memory Mapping Control (S12SMMCV1)

MM912F634

Freescale Semiconductor

173

4.28

Memory Mapping Control (S12SMMCV1)

4.28.1

Introduction

This section describes the functionality of the module mapping control (MMC) sub-block of the S12S platform. The block diagram

of the MMC is shown in Figure 47.

The MMC module controls the multi-master priority accesses (BDM and CPU), the selection of internal resources. Internal buses,

including internal memories and peripherals, are controlled in this module. The local address space for each master is translated

to a global memory space using the PPAGE register.

4.28.1.1

Terminology

4.28.1.2

Features

The main features of this block are:

•

Paging capability to support a global 256 Kilobytes memory address space

•

Bus arbitration between the masters CPU, BDM to different resources (internal and peripherals). Note: resources are

also called targets.

•

MCU operation mode control

•

MCU security control

•

Separate memory map schemes for each master CPU, BDM

•

Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong

to any of the on-chip modules) in single-chip modes

Table 238. Acronyms and Abbreviations

Logic level “1”

Voltage that corresponds to Boolean true state

Logic level “0”

Voltage that corresponds to Boolean false state

Represents hexadecimal number

Represents logic level ’don’t care’

byte

8-bit data

word

16-bit data

local address

based on the 64 Kilobytes Memory Space (16-bit address)

global address

based on the 256 Kilobytes Memory Space (18-bit address)

Aligned address

Address on even boundary

Mis-aligned address

Address on odd boundary

Bus Clock

System Clock. Refer to CRG Block Guide.

single-chip modes

Normal Single-chip mode

Special Single-chip mode

normal modes

Normal Single-chip mode

special modes

Special Single-chip mode

Normal Single-chip mode

Special Single-chip mode

Unimplemented areas

Areas which are accessible by the PPAGE, and not implemented

MCU

Micro-Controller Unit

NVM

Non-volatile Memory; Flash EEPROM or ROM

IFR

NVM Information Row. Refer to FTSR Block Guide

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