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BQ76PL455APFCT Datasheet(PDF) 110 Page - Texas Instruments |
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BQ76PL455APFCT Datasheet(HTML) 110 Page - Texas Instruments |
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110 / 125 page  VSENSE15 VSENSE16 VSENSE14 BAT16S_F R16 75 Ÿ R69 100 Ÿ C16 Z16 6.2 V BAT0 1 Q16 60 V R15 75 Ÿ R70 100 k R88 2 NŸ R76 C15 1 Q15 60 V R22 100 NŸ R89 2 NŸ R24 100 V 1 F BAT0 BAT15_F BAT14_F Z15 100 V 1 F 100 Ÿ EQ16 100 Ÿ EQ15 6.2 V Copyright © 2016, Texas Instruments Incorporated 110 bq76PL455A SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Typical Application (continued) Figure 38. Cell Balancing Circuit 8.2.2.4 Balance FET Select the Balance FET (Q15 and Q16) based on the following criteria: 1. The VDS must be selected based on derating requirements determined by the stack voltage. 2. VGS must be as large as possible and preferably have ESD protection from gate to source. This protects the part during hot plug. 3. The VGS threshold is of concern only if the discharge resistors are going to be turned on at low-battery voltages. The 2V7002K is recommended because of its 60 VDS, ± 20 VGS, and the gate is ESD protected with an internal zener diode. RDS value is of little consideration with the discharge currents for this application. Power dissipation of the FET will be a function of discharge current selected and the resistance value of FET at that worst-case condition, usually at hot temperature. I2R will be the power dissipated. Take care in selecting size if using very small packages. The VGS resistor (R77 and R85) ensures that the gate of the FET is turned off and does not float into a linear or on state causing excessive leakage currents on that cell in case of FET failure or PCB open. A series resistor between the EQ pin and the FET gate limits current going into the FET during hot plug or other transient events. |
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