BQ76PL455APFCT datasheet(114/125 Pages) TI1

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114

bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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NPN LDO Supply (continued)

Allowing for the lowest possible module voltage (VBAT min) of 12 V, using VP max = 5.5 V, VCE_SAT = 0.25 V

(from transistor datasheet) and maximum load current (bq76PL455A IACTIVE max + any additional load connected

to VP)

≈7 mA, results in R max ≈1.464 kΩ.

The R78 and R80 series resistors in the VDIG and VIO supplies (respectively) isolate large load capacitance

from the voltage regulator to help with loop stability.

Connect a filter on the VP supply (R23 and C36) for stability. Use R23 = 390 mΩ and C36 = 4.7 µF.

9.1.1 External Supply

The bq76PL455A also supports using an external supply for VDIG and VIO. Connect the external supply to these

inputs and disable the internal regulator by setting REG_DISABLE = 1 in DEVCONFIG register (address 14).

9.1.2 Handling of Supplies in Shutdown Mode

If the NPN circuit is not used (external supply), VP and VDIG should be turned off immediately after entering

SHUTDOWN mode. Removing the VP and VDIG supplies places the device in SHUTDOWN mode.

While in SHUTDOWN mode, VIO and any other external supply indirectly connected to the communication, fault,

GPIO and AUX inputs must be turned off or disabled to avoid back powering the device through internal ESD

structures. The bq76PL455A immediately enters reset when VIO is removed.

9.1.3 AFE Output RC Filter

The bq76PL455A AFE output requires an RC-filter circuit comprised of a 1-kΩ series resistor (internal to the

device) and an external capacitor on OUT1 (C44). OUT1 and OUT2 must be connected together externally. The

simple first-order RC filter provides a limited amount of noise filtering before the signal is converted by the

integrated ADC. Each input channel is converted sequentially according to the channel conversion time. For

example: ADC_PERIOD_VOL, programmed in register 62, see Register Maps, and the OUT1 and OUT2 voltage

must change quickly and settle to the new measured channel value within this time. The RC filter, while reducing

noise, slows the settling speed of the OUT1 and OUT2 voltage to the ADC and must be selected as a tradeoff

between noise cancellation and accuracy degradation. Selecting too much capacitance prevents OUT1 from

settling to the required accuracy within the programmed-channel conversion period.

Ideally, to maximize measurement accuracy, the AFE output must settle to within < 1/2 of the ADC LSB. The

worst case condition is one where the AFE output has to move the full range that is possible in the system. For

example, when an extreme imbalance condition exists or if there is a broken cell sense connection, the swing

may exceed 4.2 V. In typical conditions, where cell-to-cell variation is within 100 mV, the AFE output does not

need the extreme settling time when the new channel is selected. Select the capacitor value based on the

maximum channel-to-channel voltage transition and the actual available settling time, which is dependent on the

conversion period of the programmed channel and oversampling mode, if oversampling is programmed.

A value of 390 pF provides best accuracy with a 60-µS ADC conversion period and 8× oversampling (on the

same channel before changing channels – CMD_OVS_CYCLE = 0).

For help in selecting C44 for other sampling periods and modes or when it is desired to sample a mixture of

channel types (for example: temperature, internal test voltages as well as external cells), please contact Texas

Instruments through your FAE.

BQ76PL455APFCT Datasheet(PDF) 114 Page - Texas Instruments

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