BQ76PL455APFCT datasheet(115/125 Pages) TI1

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115

bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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10 Layout

10.1 Layout Guidelines

Since the bq76PL455A measures small changes in voltage, care must be taken in the layout of signals to and

from the device to avoid coupling noise onto sensitive inputs. The layout of ground and power connections, as

well as communication signals should also be made carefully.

10.1.1 Grounding

The bq76PL455A has three analog ground pins: AGND1, AGND2, and AGND3. AGND1 is a general-purpose

analog ground associated with the integrated linear regulator controller VP, while AGND2 and AGND3 are quiet

analog grounds for the 2.5-V reference, ADC, AFE, and Secondary Protector (window comparators) circuitry. The

bq76PL455A device also has three DGND pins for the digital core and one CGND pin for the differential

communications I/Os.

Creation of a good ground plane in the layout is crucial to getting optimal performance from the part. A good

ground plane on a dedicated layer will improve measurement accuracy, reduce noise, and provide the necessary

ESD, EMI, and EMC performance. There is a strong recommendation to have a minimum of four layers in the

PCB, with one fully dedicated as an unbroken VSS plane (except thermal reliefs). Avoid placing tracks on this

layer to maintain the unbroken integrity of the plane structure.

All seven device grounds should connect to the ground plane with as short as possible track sections to minimize

the effects of stray inductance on noise performance.

If more than one bq76PL455A is included on a single PCB assembly, each will require its own plane in the area

surrounding the device. This is required because each device has its own VSS reference, often separated by

more than 60 V from VSS-to-VSS of adjacent ICs in the stack. These can exist on the same physical layer, with

correct separation to meet creepage and clearance requirements.

Although the plane is employed as a solid GND reference with all grounds connected to it, good layout practice

still requires locating any decoupling capacitors as close to the pin they are associated with as possible. This

reduces inductance and keeps the loop area as small as possible, which in turn keeps the capacitors as effective

as possible in reducing noise.

In this document, the reference term for combined grounds connected to the ground plane is ground or GND.

10.1.2 Differential Communications

The bq76PL455A uses two differential communications links to transmit signals between ICs in a stack.

Employing differential links provides superior noise immunity. The base device then translates the differential

signals back to a single-ended signal.

It is important to maintain the signal integrity of each differential pair to maximize immunity to interfering signals

from external sources.

1. Keep wires and PCB traces as short as possible. Do not exceed datasheet recommendations.

2. For any single-signal pair between two nodes (ICs), individual wires and traces should have the same length.

3. Unshielded, twisted-pair wiring is required for any cable runs.

4. Run PCB traces in parallel, on the same layer, without any other traces or planes in between. Long runs

should avoid noisy traces and/or be stitched at intervals similar to twisted-pair wire.

5. Use high-quality capacitors for voltage isolation between ICs and place in close physical proximity to each

other as part of the parallel-track layout.

10.2 Layout Example

To ensure the best possible accuracy performance, TI recommends to follow some basic layout guidelines for

the bq76PL455A to provide best EMI and BCI performance. The isolation caps must be placed close to the edge

of the board. The Common Mode Chokes must be close to the daisy-chain cable connector to provide a high-

impedance path to common-mode noise as it enters the board. Place the series resistors and TVS diodes next to

the bq76PL455A.

BQ76PL455APFCT Datasheet(PDF) 115 Page - Texas Instruments

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