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ELANSC520 Datasheet(PDF) 25 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 25 Page - Advanced Micro Devices

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Configuration Register Overview
Élan™SC520 Microcontroller Register Set Manual
1-5
UART Serial Ports
CC0–CC6h
UART 1 General Control
UART1CTL
CC0h
page 18-3
UART 1 General Status
UART1STA
CC1h
page 18-4
UART 1 FIFO Control Shadow
UART1FCRSHAD
CC2h
page 18-5
UART 2 General Control
UART2CTL
CC4h
page 18-3
UART 2 General Status
UART2STA
CC5h
page 18-4
UART 2 FIFO Control Shadow
UART2FCRSHAD
CC6h
page 18-5
Synchronous Serial Interface
CD0–CD4h
SSI Control
SSICTL
CD0h
page 19-2
SSI Transmit
SSIXMIT
CD1h
page 19-4
SSI Command
SSICMD
CD2h
page 19-5
SSI Status
SSISTA
CD3h
page 19-6
SSI Receive
SSIRCV
CD4h
page 19-7
Programmable Interrupt Controller
D00–D5Ah
Interrupt Control
PICICR
D00h
page 12-4
Master PIC Interrupt Mode
MPICMODE
D02h
page 12-6
Slave 1 PIC Interrupt Mode
SL1PICMODE
D03h
page 12-8
Slave 2 PIC Interrupt Mode
SL2PICMODE
D04h
page 12-9
Software Interrupt 16–1 Control
SWINT16_1
D08h
page 12-10
Software Interrupt 22–17/NMI Control
SWINT22_17
D0Ah
page 12-13
Interrupt Pin Polarity
INTPINPOL
D10h
page 12-15
PCI Host Bridge Interrupt Mapping
PCIHOSTMAP
D14h
page 12-17
ECC Interrupt Mapping
ECCMAP
D18h
page 12-19
GP Timer 0 Interrupt Mapping
GPTMR0MAP
D1Ah
page 12-21
GP Timer 1 Interrupt Mapping
GPTMR1MAP
D1Bh
page 12-21
GP Timer 2 Interrupt Mapping
GPTMR2MAP
D1Ch
page 12-21
PIT 0 Interrupt Mapping
PIT0MAP
D20h
page 12-21
PIT 1 Interrupt Mapping
PIT1MAP
D21h
page 12-21
PIT 2 Interrupt Mapping
PIT2MAP
D22h
page 12-21
UART 1 Interrupt Mapping
UART1MAP
D28h
page 12-21
UART 2 Interrupt Mapping
UART2MAP
D29h
page 12-21
PCI Interrupt A Mapping
PCIINTAMAP
D30h
page 12-21
PCI Interrupt B Mapping
PCIINTBMAP
D31h
page 12-21
PCI Interrupt C Mapping
PCIINTCMAP
D32h
page 12-21
PCI Interrupt D Mapping
PCIINTDMAP
D33h
page 12-21
DMA Buffer Chaining Interrupt Mapping
DMABCINTMAP
D40h
page 12-21
SSI Interrupt Mapping
SSIMAP
D41h
page 12-21
Watchdog Timer Interrupt Mapping
WDTMAP
D42h
page 12-21
RTC Interrupt Mapping
RTCMAP
D43h
page 12-21
Write-Protect Violation Interrupt Mapping
WPVMAP
D44h
page 12-21
AMDebug™ Technology RX/TX Interrupt Mapping
ICEMAP
D45h
page 12-21
Table 1-1
Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued)
Register Name
Mnemonic
MMCR Offset Page Number



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