ELANSC520 datasheet(47/440 Pages) AMD

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Reset Generation Registers

Élan™SC520 Microcontroller Register Set Manual

3-5

Reset Status (RESSTA)

Memory-Mapped

MMCR Offset D74h

This register provides status information on the various reset sources implemented in the ÉlanSC520 microcontroller:

emulated system control processor (SCP)-generated reset, CPU shutdown, AMDebug technology system reset,

AMDebug technology hard reset, watchdog timer, PWRGOOD signal, and PRGRESET signal.

Bit Definitions

Bit

Reserved

SCP_RST_

DET

ICE_HRST_

DET

ICE_SRST_

DET

WDT_RST_

DET

SD_RST_

DET

PRGRST_

DET

PWRGOOD_

DET

Reset

00000001

R/W

RSV

R/W!

Bit

Name

Function

Reserved

This bit field should be written to 0 for normal system operation.

SCP_RST_

DET

SCP Reset Detect

This bit is set when a soft reset is generated by the SCP emulation logic. Software clears this

bit by writing a 1.

0 = No SCP reset was detected.

1 = The CPU soft reset event was from an SCP reset command. (See the SCPCMD register

description on page 3-8).

A soft reset event clears the NMI_ENB bit in the PICICR register (see page 12-4). This allows

software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset.

ICE_HRST_

DET

AMDebug™ Technology Hard Reset Detect

This bit is set when a AMDebug technology hard reset is detected. Software clears this bit by

writing a 1.

0 = No AMDebug technology hard reset was detected.

1 = The CPU hard reset event was from an AMDebug technology hard reset.

ICE_SRST_

DET

AMDebug™ Technology System Reset Detect

This bit is set when an AMDebug technology system reset is detected. Software clears this bit

by writing a 1.

0 = No AMDebug technology system reset was detected.

1 = The system reset event was from an AMDebug technology system reset.

If the PRG_RST_ENB bit is 1 in the RESCFG register (see page 3-3), an AMDebug

technology system reset results in a programmable reset in which the SDRAM configuration

is maintained.

WDT_RST_

DET

Watchdog Timer Reset Detect

This bit is set when a watchdog timer system reset is detected. Software clears this bit by

writing a 1.

0 = No watchdog timer reset was detected.

1 = The system reset event was from a watchdog timer time-out.

If the PRG_RST_ENB bit is 1 in the RESCFG register (see page 3-3), a watchdog timer reset

results in a programmable reset in which the SDRAM configuration is maintained.

ELANSC520 Datasheet(PDF) 47 Page - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 47 Page - Advanced Micro Devices

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