ELANSC520 datasheet(38/440 Pages) AMD

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System Address Mapping Registers

2-6

Élan™SC520 Microcontroller Register Set Manual

These registers can be used to map windows of memory address space to SDRAM, ROM, PCI bus, or GP bus; or

to map windows of I/O space to the GP bus. These registers are also used to apply noncacheability, write-protect,

and nonexecutable attributes to SDRAM and ROM regions.

Bit Definitions

Bit

Name

Function

–29

TARGET[2

–0]

Target of the PARx Window

This bit field defines the target (destination) of the PARx window being configured.

If no PARx window is enabled (i.e., the TARGET bit field is 000b in all PARx registers), the

default memory map for the lower 1 Gbyte address range (00000000h–3FFFFFFFh) is either

SDRAM (if enabled) or PCI.

Accesses to any external GP bus devices or devices connected to ROMCS1 or ROMCS2

require a PARx window to be enabled and configured to access them.

000 = The window is disabled. All other bits in the PARx register are ignored.

001 = The window targets a GP bus I/O region. This is the only I/O space access possible

through a PARx window. All other settings refer to the memory address space. For GP

bus windows, the ATTR bit field selects a GP bus chip select. See the programming

notes for this register, on page 2-8, for GP-bus I/O address restrictions.

010 = The window targets a GP bus memory region. For GP bus windows, the ATTR bit field

selects a GP bus chip select.

011 = The window targets a PCI bus memory region. Only PAR0 and PAR1 support a PCI bus

memory region as a target. Define a PCI bus window only when attempting to forward

cycles to the PCI bus in the lower 256 Mbyte address range (00000000h to

0FFFFFFFh).

100 = The window targets a BOOTCS region (boot ROM or Flash memory device).

The ÉlanSC520 microcontroller forces the BOOTCS signal active at system reset, but

the boot code must initialize a PARx register to decode the required space for the

ROM. Refer to the

Élan™SC520 Microcontroller User’s Manual, order #22004, for

details on configuring the boot ROM during system initialization.

101 = The window targets a ROMCS1 region (ROM or Flash memory devices).

110 = The window targets a ROMCS2 region (ROM or Flash memory devices).

111 = The window targets an SDRAM region. A PARx register is not required to access

SDRAM. Target an SDRAM region only when applying one of the attributes described

in the ATTR bit field.

ELANSC520 Datasheet(PDF) 38 Page - Advanced Micro Devices

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