ELANSC520 datasheet(70/440 Pages) AMD

70 / 440 page

PCI Bus Host Bridge Registers

6-6

Élan™SC520 Microcontroller Register Set Manual

Programming Notes

This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset

is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3).

Interrupt status bits are set whenever the associated event occurs regardless of the corresponding interrupt enable bit.

For a host bridge NMI to propagate to the CPU, host bridge NMIs must be enabled via the PCI_NMI_ENB bit in the

PCIHOSTMAP register (see page 12-17), and NMIs must be enabled via the NMI_ENB bit in the PICICR register

(see page 12-4).

Before host bridge interrupts are enabled, the PCIHOSTMAP register (see page 12-17) must be configured to route

the interrupt to the appropriate interrupt request level and priority.

The interrupt enabled via the GNT_TO_INT_ENB bit in the SYSARBCTL register (see page 5-2) shares the

interrupt controller input used by host bridge interrupts.

T_DPER_

IRQ_ENB

Target Data Parity Interrupt Enable

This bit allows data parity errors detected by the target controller to generate an interrupt.

0 = Data parity errors do not generate an interrupt.

1 = Data parity errors generate an interrupt.

Bit

Name

Function

ELANSC520 Datasheet(PDF) 70 Page - Advanced Micro Devices