ELANSC520 datasheet(97/440 Pages) AMD

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SDRAM Controller Registers

Élan™SC520 Microcontroller Register Set Manual

7-9

ECC Control (ECCCTL)

Memory-Mapped

MMCR Offset 20h

This register controls all the error correction code (ECC) functions.

Note: A programmable reset preserves this register’s state.See the PRG_RST_ENB bit description on page 3-3.

Bit Definitions

Programming Notes

This register (ECCCTL) should be modified only when the write buffer and the read-ahead feature of the read buffer

are disabled in the DBCTL register (see page 8-3).

Before ECC multi-bit or single-bit interrupts are enabled, the ECCMAP register (see page 12-19) must be configured

to route the interrupt to the appropriate interrupt request level and priority.

Bit

Reserved

MULT_INT_

ENB

SGL_INT_

ENB

ECC_ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

–3

Reserved

This bit field should be written to 0 for normal system operation.

MULT_INT_

ENB

Enable Multi-Bit Interrupt

This bit enables the ECC non-maskable interrupt (NMI) source to go active on the detection of

a multi-bit error.

0 = Disabled

1 = Enabled

The ECC NMI source must also be enabled via the ECC_NMI_ENB bit in the ECCMAP

1SGL_INT_

ENB

Enable Single-bit Interrupt

This bit enables the ECC maskable interrupt source to go active on the detection of a single-

bit error.

0 = Disabled

1 = Enabled

The ECC single-bit interrupt source must also be mapped to an interrupt channel via the

ECC_IRQ_MAP bit field in the ECCMAP register (see page 12-20).

ECC_ENB

ECC Enable for All Four Banks

This bit enables ECC for all four banks.

0 = Disabled

1 = Enabled

When ECC is enabled, writes to SDRAM include a write of the error correction code (ECC) to

the SDRAM device’s ECC location, and reads from SDRAM are checked for a correct ECC.

Any ECC mismatch is reported in the appropriate registers and the appropriate interrupt is

generated if enabled via the MULT_INT_ENB and SGL_INT_ENB bits.

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