ELANSC520 datasheet(59/440 Pages) AMD

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System Arbitration Registers

Élan™SC520 Microcontroller Register Set Manual

5-3

PCI Bus Arbiter Status (PCIARBSTA)

Memory-Mapped

MMCR Offset 71h

This register provides grant time-out status of the PCI bus arbiter.

Bit Definitions

Programming Notes

Bit

GNT_TO_

STA

Reserved

GNT_TO_ID[3–0]

Reset

00001111

R/W

R/W!

RSV

Bit

Name

Function

GNT_TO_STA

PCI Bus Arbiter Grant Time-Out Status

This bit is set when the PCI bus arbiter detects a grant time-out (transaction not started within

16 clocks of the PCI bus going idle). The GNT that was asserted when this condition occurs

can be read in the GNT_TO_ID bit field.

0 = Grant time-out has not occurred.

1 = Grant time-out has occurred.

This bit (GNT_TO_STA) is cleared by writing a 1.

This bit operates regardless of the corresponding interrupt enable bit (GNT_TO_INT_ENB in

the SYSARBCTL register, see page 5-2).

When enabled as an interrupt, this source shares the interrupt controller input used by any

host bridge interrupts enabled in the HBTGTIRQCTL and HBMSTIRQCTL registers (see

page 6-5 and page 6-9).

6–4

Reserved

This bit field should be written to 0 for normal system operation.

3–0

GNT_TO_ID

[3–0]

PCI Bus Arbiter Grant Time-Out Identification

This bit field identifies which GNT was asserted when the PCI arbiter detected a grant time-

out. This bit field is reset to ones by writing a one to the GNT_TO_STA bit.

0000 = GNT0 was asserted when a grant time-out was detected.

0001 = GNT1 was asserted when a grant time-out was detected.

0010 = GNT2 was asserted when a grant time-out was detected.

0011 = GNT3 was asserted when a grant time-out was detected.

0100 = GNT4 was asserted when a grant time-out was detected.

0101–1101 = Reserved

1110 = The Am5x86 CPU GNT was asserted when a grant time-out was detected.

1111 = No grant time-out was detected, or GNT was asserted when a grant time-out was

detected but not latched.

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