ELANSC520 datasheet(94/440 Pages) AMD

94 / 440 page

SDRAM Controller Registers

7-6

Élan™SC520 Microcontroller Register Set Manual

Programming Notes

This register (DRCCFG) should be modified only when the write buffer and the read-ahead feature of the read buffer

are disabled in the DBCTL register (see page 8-3).

Before changing the BNKx_BNK_CNT or BNKx_COLWDTH bit fields, software must issue an All Banks Precharge

command to the SDRAM devices via the OPMODE_SEL bit field in the DBCCTL register (see page 7-3). This

command returns the SDRAM devices to an idle state and also clears the SDRAM controller’s page table entries.

BNK1_BNK_

CNT

Bank 1 Internal SDRAM Bank Count

This bit specifies the number of internal banks supported by the SDRAM devices.

0 = 2-bank device

1 = 4-bank device

Reserved

This bit field should be written to 0 for normal system operation.

–4

BNK1_

COLWDTH[1–0]

Bank 1 Column Address Width

These two bits specify the column address width of the SDRAM devices populated in Bank 1.

00 = 8-bit column address

01 = 9-bit column address

10 = 10-bit column address

11 = 11-bit column address

BNK0_BNK_

CNT

Bank 0 Internal SDRAM Bank Count

This bit specifies the number of internal banks supported by the SDRAM devices.

0 = 2-bank device

1 = 4-bank device

Reserved

This bit field should be written to 0 for normal system operation.

–0

BNK0_

COLWDTH[1–0]

Bank 0 Column Address Width

These two bits specify the column address width of the SDRAM devices populated in Bank 0.

00 = 8-bit column address

01 = 9-bit column address

10 = 10-bit column address

11 = 11-bit column address

Bit

Name

Function

ELANSC520 Datasheet(PDF) 94 Page - Advanced Micro Devices

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