ELANSC520 datasheet(60/440 Pages) AMD

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System Arbitration Registers

5-4

Élan™SC520 Microcontroller Register Set Manual

System Arbiter Master Enable (SYSARBMENB)

Memory-Mapped

MMCR Offset 72h

This register selects the masters that are enabled for arbitration.

Bit Definitions

Bit

Reserved

Reset

00000000

R/W

RSV

Bit

Reserved

REQ4_ENB REQ3_ENB REQ2_ENB REQ1_ENB REQ0_ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

15–5

Reserved

This bit field should be written to 0 for normal system operation.

REQ4_ENB

PCI Bus Arbiter Request #4 Enable

This bit enables the PCI master request connected to the REQ4 pin. If this request is

disabled, the PCI bus arbiter does not assert GNT4 to allow the PCI master connected to

REQ4 and GNT4 to access the PCI bus.

0 = The PCI master request connected to the REQ4 pin is disabled.

1 = The PCI master request connected to the REQ4 pin is enabled.

REQ3_ENB

PCI Bus Arbiter Request #3 Enable

This bit enables the PCI master request connected to the REQ3 pin. If this request is

disabled, the PCI bus arbiter does not assert GNT3 to allow the PCI master connected to the

REQ3 and GNT3 pins to access the PCI bus.

0 = The PCI master request connected to the REQ3 pin is disabled.

1 = The PCI master request connected to the REQ3 pin is enabled.

REQ2_ENB

PCI Bus Arbiter Request #2 Enable

This bit enables the PCI master request connected to the REQ2 pin. If this request is

disabled, the PCI bus arbiter does not assert GNT2 to allow the PCI master connected to the

REQ2 and GNT2 pins to access the PCI bus.

0 = The PCI master request connected to the REQ2 pin is disabled.

1 = The PCI master request connected to the REQ2 pin is enabled.

REQ1_ENB

PCI Bus Arbiter Request #1 Enable

This bit enables the PCI master request connected to the REQ1 pin. If this request is

disabled, the PCI bus arbiter does not assert GNT1 to allow the PCI master connected to the

REQ1 and GNT1 pins to access the PCI bus.

0 = The PCI master request connected to the REQ1 pin is disabled.

1 = The PCI master request connected to the REQ1 pin is enabled.

ELANSC520 Datasheet(PDF) 60 Page - Advanced Micro Devices

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