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ELANSC520 Datasheet(PDF) 30 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 30 Page - Advanced Micro Devices

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Configuration Register Overview
1-10
Élan™SC520 Microcontroller Register Set Manual
1.3
PCI HOST BRIDGE INDEXED CONFIGURATION REGISTERS
The ÉlanSC520 microcontroller’s PCI Host Bridge supports the required PCI configuration
space header registers, plus a Host Bridge-specific Master Retry Time-Out
(PCIMRETRYTO) register defined in the PCI configuration space. Note that additional
microcontroller-specific PCI Host Bridge configuration registers are provided in the MMCR
space (see Table 1-1).
PCI indexed registers are accessed via two 32-bit direct-mapped I/O locations: Port 0CF8h
and Port 0CFCh. The PCI configuration mechanism can be used to access either the Host
Bridge-specific PCI indexed registers, or the device-specific PCI indexed registers for any
Floating Point Error Interrupt Clear
FPUERRCLR
F0h
page 12-61
UART 2
02F8–02FFh
UART 2 Transmit Holding
UART2THR
02F8h
page 18-7
UART 2 Receive Buffer
UART2RBR
02F8h
page 18-8
UART 2 Baud Clock Divisor Latch LSB
UART2BCDL
02F8h
page 18-9
UART 2 Baud Clock Divisor Latch MSB
UART2BCDH
02F9h
page 18-10
UART 2 Interrupt Enable
UART2INTENB
02F9h
page 18-11
UART 2 Interrupt ID
UART2INTID
02FAh
page 18-12
UART 2 FIFO Control
UART2FCR
02FAh
page 18-15
UART 2 Line Control
UART2LCR
02FBh
page 18-17
UART 2 Modem Control
UART2MCR
02FCh
page 18-19
UART 2 Line Status
UART2LSR
02FDh
page 18-21
UART 2 Modem Status
UART2MSR
02FEh
page 18-23
UART 2 Scratch Pad
UART2SCRATCH
02FFh
page 18-25
UART 1
03F8–03FFh
UART 1 Transmit Holding
UART1THR
03F8h
page 18-7
UART 1 Receive Buffer
UART1RBR
03F8h
page 18-8
UART 1 Baud Clock Divisor Latch LSB
UART1BCDL
03F8h
page 18-9
UART 1 Baud Clock Divisor Latch MSB
UART1BCDH
03F9h
page 18-10
UART 1 Interrupt Enable
UART1INTENB
03F9h
page 18-11
UART 1 Interrupt ID
UART1INTID
03FAh
page 18-12
UART 1 FIFO Control
UART1FCR
03FAh
page 18-15
UART 1 Line Control
UART1LCR
03FBh
page 18-17
UART 1 Modem Control
UART1MCR
03FCh
page 18-19
UART 1 Line Status
UART1LSR
03FDh
page 18-21
UART 1 Modem Status
UART1MSR
03FEh
page 18-23
UART 1 Scratch Pad
UART1SCRATCH
03FFh
page 18-25
PCI Bus Configuration Space Index/Data (32-bit)
0CF8h, 0CFCh
PCI Configuration Address
PCICFGADR
0CF8h
page 6-15
PCI Configuration Data
PCICFGDATA
0CFCh
page 6-17
Configuration Base Address
CBAR
FFFCh
page 2-9
Table 1-2
Direct-Mapped I/O Registers (Continued)
Register Name
Mnemonic
I/O Address
Page Number



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