ELANSC520 datasheet(35/440 Pages) AMD

35 / 440 page

System Address Mapping Registers

Élan™SC520 Microcontroller Register Set Manual

2-3

Programming Notes

When the ÉlanSC520 microcontroller comes out of reset, the internal RTC and UARTs are enabled. If the system

application requires the use of an external RTC or UARTs, the internal devices should be disabled during the boot

process and initialization to prevent potential conflicts.

When the integrated UARTs are disabled, only the I/O space accesses associated with these peripherals are

forwarded externally. The accesses to the MMCR registers for the UARTs are not forwarded externally because

these registers are specific to the integrated peripherals. Therefore, the UART MMCR registers should not be used

while the integrated UARTs are disabled.

Even if the internal RTC or UARTs are disabled, setting the IO_HOLE_DEST bit does

not redirect accesses to the

disabled peripherals to PCI bus I/O space.

2RTC_DIS

RTC Disable

This bit causes the integrated RTC to be disabled.

0 = The integrated RTC is enabled.

1 = The integrated RTC is not used, and accesses to the RTC address space are forwarded

externally to the GP bus.

When the internal RTC is disabled, the corresponding interrupt request is not automatically

disconnected from the PIC. If an external RTC is to drive the RTC interrupt request, then all

interrupt enables in the RTCCTLB register must be cleared prior to disabling the internal RTC

(see page 17-16).

After the internal RTC is disabled, a PARx window can be defined to target a GPCSx chip

select in the RTC I/O address space. If a PARx window is not used, the external RTC must

fully decode the addresses.

UART2_DIS

UART 2 Disable

This bit causes the integrated UART 2 to be disabled.

0 = The integrated UART 2 is enabled.

1 = The integrated UART 2 is not used, and accesses to the UART 2 I/O address space are

forwarded externally to the GP bus.

When the internal UART 2 is disabled, the corresponding interrupt request is not

automatically disconnected from the PIC. If an external UART is to drive the UART 2 interrupt

request, then all interrupt enables in the UART2CTL and UART2INTENB registers must be

cleared (see page 18-3 and page 18-11).

After the internal UART 2 is disabled, a PARx window can be defined to target a GPCSx chip

select in the UART 2 I/O address space. If a PARx window is not used, the external UART

must fully decode the addresses.

UART1_DIS

UART 1 Disable

This bit causes the integrated UART 1 to be disabled.

0 = The integrated UART 1 is enabled.

1 = The integrated UART 1 is not used, and accesses to the UART 1 I/O address space are

forwarded externally to the GP bus.

When the internal UART 1 is disabled, the corresponding interrupt request is not

automatically disconnected from the PIC. If an external UART is to drive the UART 1 interrupt

request, then all interrupt enables in the UART1CTL and UART1INTENB registers must be

cleared (see page 18-3 and page 18-11).

After the internal UART 1 is disabled, a PARx window can be defined to target a GPCSx chip

select in the UART 1 I/O address space. If a PARx window is not used, the external UART

must fully decode the addresses.

Bit

Name

Function

ELANSC520 Datasheet(PDF) 35 Page - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 35 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL