ELANSC520 datasheet(92/440 Pages) AMD

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SDRAM Controller Registers

7-4

Élan™SC520 Microcontroller Register Set Manual

SDRAM Timing Control (DRCTMCTL)

Memory-Mapped

MMCR Offset 12h

This register controls the SDRAM device timing.

Note: A programmable reset preserves this register’s state. See the PRG_RST_ENB bit description on page 3-3.

Bit Definitions

Programming Notes

This register (DRCTMCTL) should be modified only when the write buffer and the read-ahead feature of the read

buffer are disabled in the DBCTL register (see page 8-3).

Bit

Reserved

CAS_LAT

RAS_PCHG_DLY[1–0]

RAS_CAS_DLY[1–0]

Reset

00011010

R/W

RSV

R/W

Bit

Name

Function

–5

Reserved

This bit field should be written to 0 for normal system operation.

CAS_LAT

SDRAM CAS Latency

This bit controls the SCASx signal latency timing to all the SDRAM banks.

0 = Cycle latency is 2T.

1 = Cycle latency is 3T (default).

Where T is 15 ns (one half of the 33-MHz clock cycle).

To make the CAS_LAT bit setting take effect, a Load Mode Register command must be issued

to the SDRAM devices via the OPMODE_SEL bit field of the DRCCTL register (see

page 7-3). Incorrect operation can occur if the CAS_LAT bit is modified and the Load Mode

–2

RAS_PCHG_

DLY[1–0]

SDRAM RAS Precharge Delay

This bit field determines the SRASx signal precharge delay.

00 = 2T

01 = 3T

10 = 4T (default)

11 = 6T

Where T is 15 ns (one half of the 33-MHz clock cycle).

–0

RAS_CAS_

DLY[1–0]

SDRAM RAS-to-CAS Delay

This bit field determines the SRASx-to-SCASx delay.

00 = 2T

01 = 3T

10 = 4T (default)

11 = Reserved

Where T is 15 ns (one half of the 33-MHz clock cycle).

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