ELANSC520 datasheet(98/440 Pages) AMD

98 / 440 page

SDRAM Controller Registers

7-10

Élan™SC520 Microcontroller Register Set Manual

ECC Status (ECCSTA)

Memory-Mapped

MMCR Offset 21h

This register maintains status of the ECC functions if ECC is enabled.

Note: A programmable reset does not preserve this register’s state.

Bit Definitions

Programming Notes

Software should write to this register (ECCSTA) only to clear the error status, and only after a status bit was read as 1.

Bit

Reserved

MBIT_ERR

SBIT_ERR

Reset

00000000

R/W

RSV

R/W!

Bit

Name

Function

–2

Reserved

This bit field should be written to 0 for normal system operation.

MBIT_ERR

Multi-Bit Error Detected

0 = The event has not occurred, or software cleared this bit by writing a 1.

1 = A multi-bit ECC error has occurred.

Software must write a 1 to clear this bit and rearm the logic that captures the physical address

where the multi-bit error occurred.

The multi-bit error physical address can be read from the ECCMBADD register (see

page 7-15).

SBIT_ERR

Single-bit ECC Error

0 = The event has not occurred, or software cleared this bit by writing a 1.

1 = A single-bit ECC error has occurred.

Software must write a 1 to clear this bit and rearm the logic that captures the physical address

and bit position where the single-bit error occurred.

The single-bit error physical address can be read from the ECCSBADD register (see

page 7-14). The single-bit error bit position can be read from the ECCCKBPOS register (see

page 7-11).

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