ELANSC520 datasheet(102/440 Pages) AMD

102 / 440 page

SDRAM Controller Registers

7-14

Élan™SC520 Microcontroller Register Set Manual

ECC Single-Bit Error Address (ECCSBADD)

Memory-Mapped

MMCR Offset 24h

This register contains the physical address of the location in SDRAM that caused a single-bit ECC error.

Note: A programmable reset does not preserve this register’s state.

Bit Definitions

Programming Notes

Bit

Reserved

SB_ADDR[27

–24]

Reset

00000000

R/W

RSV

Bit

SB_ADDR[23

–16]

Reset

00000000

R/W

Bit

SB_ADDR[15

–8]

Reset

00000000

R/W

Bit

SB_ADDR[7

–2]

Reserved

Reset

00000000

R/W

RRSV

Bit

Name

Function

–28

Reserved

This bit field should be written to 0 for normal system operation.

–2

SB_ADDR

[27

–2]

ECC Single-bit Error Address

This bit field contains the physical address (bits 27

–2) of the location where a single-bit error

occurred.

The address is captured upon the detection of a single-bit error, and the bit field is inhibited

from capturing subsequent error addresses until the SBIT_ERR bit in the ECCSTA register is

cleared by writing a 1 (see page 7-10).

Note: This register does not include byte enables (BE) from the requesting master, therefore

only doubleword resolution is provided by the indication. Use the ECCCKBPOS register to

determine which bit was in error (see page 7-11).

–0

Reserved

This bit field should be written to 0 for normal system operation.

ELANSC520 Datasheet(PDF) 102 Page - Advanced Micro Devices

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