ELANSC520 datasheet(83/440 Pages) AMD

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PCI Bus Host Bridge Registers

Élan™SC520 Microcontroller Register Set Manual

6-19

Status/Command (PCISTACMD)

I/O Address 0CF8h/0CFCh

PCI Index 04h

This register contains the PCI configuration header space command and status register bits.

Bit Definitions

Bit

PERR_DET SIG_SERR

R_MST_

ABT

R_TGT_

ABT

S_TGT_

ABT

S_DVSL_TIM[1–0]

D_PERR_

DET

Reset

00000010

R/W

R/W!

Bit

FBTB

UDFS

66M_CAP

Reserved

Reset

10000000

R/W

RRR

RSV

Bit

Reserved

SERR_ENB

Reset

00000000

R/W

RSV

Bit

Reserved

PERR_RES

Reserved

BUS_MAS

MEM_ENB

IO_ENB

Reset

00000100

R/W

RSV

R/W

RSV

R/W

Bit

Name

Function

PERR_DET

Parity Error Detected

This bit is set when a parity error is detected by the host bridge master or target controller.

0 = Parity error not detected.

1 = Parity error detected.

This bit is cleared by writing a 1.

SIG_SERR

Signaled System Error

This bit is normally used to indicate that the PCI bus agent has asserted the SERR pin,

however the host bridge does not drive SERR because the interrupt logic is integrated within

the ÉlanSC520 microcontroller.

0 = SERR pin not asserted by the host bridge.

This bit is internally fixed to 0.

ELANSC520 Datasheet(PDF) 83 Page - Advanced Micro Devices

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