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ELANSC520 Datasheet(PDF) 33 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 33 Page - Advanced Micro Devices

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Élan™SC520 Microcontroller Register Set Manual
2-1
CHAPTER
2 SYSTEM ADDRESS MAPPING
REGISTERS
2.1
OVERVIEW
This chapter describes the system memory and I/O address mapping registers of the
ÉlanSC520 microcontroller.
The system address mapping register set consists of 18 memory-mapped configuration
region (MMCR) registers and one direct-mapped I/O register used to define the memory
and I/O map in an ÉlanSC520 microcontroller-based system, and to control specific
attributes of SDRAM and ROM regions. See the
Élan™SC520 Microcontroller User’s
Manual, order #22004, for details about memory and I/O space.
Table 2-1 and Table 2-2 list each type of memory and I/O space register in offset order, with
the corresponding description’s page number.
2.2
REGISTERS
Table 2-1
System Address Mapping MMCR Registers
Register Name
Mnemonic
MMCR Offset
Page Number
Address Decode Control
ADDDECCTL
80h
page 2-2
Write-Protect Violation Status
WPVSTA
82h
page 2-4
Programmable Address Region 0
PAR0
88h
page 2-5
Programmable Address Region 1
PAR1
8Ch
page 2-5
Programmable Address Region 2
PAR2
90h
page 2-5
Programmable Address Region 3
PAR3
94h
page 2-5
Programmable Address Region 4
PAR4
98h
page 2-5
Programmable Address Region 5
PAR5
9Ch
page 2-5
Programmable Address Region 6
PAR6
A0h
page 2-5
Programmable Address Region 7
PAR7
A4h
page 2-5
Programmable Address Region 8
PAR8
A8h
page 2-5
Programmable Address Region 9
PAR9
ACh
page 2-5
Programmable Address Region 10
PAR10
B0h
page 2-5
Programmable Address Region 11
PAR11
B4h
page 2-5
Programmable Address Region 12
PAR12
B8h
page 2-5
Programmable Address Region 13
PAR13
BCh
page 2-5
Programmable Address Region 14
PAR14
C0h
page 2-5
Programmable Address Region 15
PAR15
C4h
page 2-5
Table 2-2
System Address Mapping Direct-Mapped Register
Register Name
Mnemonic
I/O Address
Page Number
Configuration Base Address
CBAR
FFFCh
page 2-9



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