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ELANSC520 Datasheet(PDF) 29 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 29 Page - Advanced Micro Devices

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Configuration Register Overview
Élan™SC520 Microcontroller Register Set Manual
1-9
General 1
GPDMAGR1
0084h
page 11-66
General 2
GPDMAGR2
0085h
page 11-67
General 3
GPDMAGR3
0086h
page 11-68
Slave DMA Channel 0 Page
GPDMA0PG
0087h
page 11-69
General 4
GPDMAGR4
0088h
page 11-70
Master DMA Channel 6 Page
GPDMA6PG
0089h
page 11-71
Master DMA Channel 7 Page
GPDMA7PG
008Ah
page 11-72
Master DMA Channel 5 Page
GPDMA5PG
008Bh
page 11-73
General 5
GPDMAGR5
008Ch
page 11-74
General 6
GPDMAGR6
008Dh
page 11-75
General 7
GPDMAGR7
008Eh
page 11-76
General 8
GPDMAGR8
008Fh
page 11-77
System Control Port A
SYSCTLA
0092h
page 3-9
Slave 1 PIC
00A0–00A1h
Slave 1 PIC Interrupt Request
S1PICIR
00A0h
page 12-49
Slave 1 PIC In-Service
S1PICISR
00A0h
page 12-50
Slave 1 PIC Initialization Control Word 1
S1PICICW1
00A0h
page 12-51
Slave 1 PIC Operation Control Word 2
S1PICOCW2
00A0h
page 12-53
Slave 1 PIC Operation Control Word 3
S1PICOCW3
00A0h
page 12-55
Slave 1 PIC Initialization Control Word 2
S1PICICW2
00A1h
page 12-57
Slave 1 PIC Initialization Control Word 3
S1PICICW3
00A1h
page 12-58
Slave 1 PIC Initialization Control Word 4
S1PICICW4
00A1h
page 12-59
Slave 1 PIC Interrupt Mask
S1PICINTMSK
00A1h
page 12-60
Master DMA
00C0–00DEh
Master DMA Channel 4 Memory Address
GPDMA4MAR
00C0h
page 11-78
Master DMA Channel 4 Transfer Count
GPDMA4TC
00C2h
page 11-79
Master DMA Channel 5 Memory Address
GPDMA5MAR
00C4h
page 11-80
Master DMA Channel 5 Transfer Count
GPDMA5TC
00C6h
page 11-81
Master DMA Channel 6 Memory Address
GPDMA6MAR
00C8h
page 11-82
Master DMA Channel 6 Transfer Count
GPDMA6TC
00CAh
page 11-83
Master DMA Channel 7 Memory Address
GPDMA7MAR
00CCh
page 11-84
Master DMA Channel 7 Transfer Count
GPDMA7TC
00CEh
page 11-85
Master DMA Channel 4–7 Status
MSTDMASTA
00D0h
page 11-86
Master DMA Channel 4–7 Control
MSTDMACTL
00D0h
page 11-87
Master Software DRQ(n) Request
MSTDMASWREQ
00D2h
page 11-89
Master DMA Channel 4–7 Mask
MSTDMAMSK
00D4h
page 11-90
Master DMA Channel 4–7 Mode
MSTDMAMODE
00D6h
page 11-91
Master DMA Clear Byte Pointer
MSTDMACBP
00D8h
page 11-93
Master DMA Controller Reset
MSTDMARST
00DAh
page 11-94
Master DMA Controller Temporary
MSTDMATMP
00DAh
page 11-95
Master DMA Mask Reset
MSTDMAMSKRST
00DCh
page 11-96
Master DMA General Mask
MSTDMAGENMSK
00DEh
page 11-97
Table 1-2
Direct-Mapped I/O Registers (Continued)
Register Name
Mnemonic
I/O Address
Page Number



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