ELANSC520 datasheet(76/440 Pages) AMD

76 / 440 page

PCI Bus Host Bridge Registers

6-12

Élan™SC520 Microcontroller Register Set Manual

Host Bridge Master Interrupt Status (HBMSTIRQSTA)

Memory-Mapped

MMCR Offset 68h

This register contains host bridge master controller interrupt status bits and command interrupt identification.

Bit Definitions

Bit

Reserved

M_CMD_IRQ_ID[3–0]

Reset

00000000

R/W

RSV

Bit

Reserved

M_RTRTO_

IRQ_STA

M_TABRT_

IRQ_STA

M_MABRT_

IRQ_STA

M_SERR_

IRQ_STA

M_RPER_

IRQ_STA

M_DPER_

IRQ_STA

Reset

00000000

R/W

RSV

R/W!

Bit

Name

Function

–12

Reserved

This bit field should be written to 0 for normal system operation.

–8

M_CMD_

IRQ_ID[3–0]

Master Command Interrupt Identification

This bit field reports the command of the transaction during which the master controller

detected an error condition. This bit field is valid only when an interrupt status bit is set. It is

cleared when the interrupt status is cleared.

0000 = The command was not latched. For example, the command is not latched if multiple

interrupts are pending and one interrupt status was cleared.

0001 = Special Cycle (not used by the ÉlanSC520 microcontroller).

0010 = I/O Read.

0011 = I/O Write.

0100–0101 = Reserved.

0110 = Memory Read.

0111 = Memory Write.

1000–1001 = Reserved.

1010 = Configuration Read.

1011 = Configuration Write.

1100 = Memory Read Multiple (not used by the ÉlanSC520 microcontroller).

1101 = Dual-Address Cycle (not used by the ÉlanSC520 microcontroller).

1110 = Memory Read Line (not used by the ÉlanSC520 microcontroller).

1111 = Memory Write and Invalidate (not used by the ÉlanSC520 microcontroller).

If multiple errors are detected, only the command of the first error is latched. When multiple

error interrupts are pending, there is no indication of which interrupt the command

corresponds to.

The MSTINTADD register (see page 6-14) contains the address of the transaction during

which the master controller detected an error condition.

–6

Reserved

This bit field should be written to 0 for normal system operation.

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