ELANSC520 datasheet(46/440 Pages) AMD

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Reset Generation Registers

3-4

Élan™SC520 Microcontroller Register Set Manual

Programming Notes

After a PWRGOOD reset, the programmable system reset feature is disabled and can be enabled only by software

writing a 1 to the PRG_RST_ENB bit. If the PRGRESET pin is asserted after it has been enabled as a programmable

reset, it causes a programmable reset, which does not reset the SDRAM controller configuration or contents. This

allows the contents of SDRAM to be preserved.

The PWRGOOD pin always has higher priority than the PRGRESET pin. For example, if the PRGRESET pin is

asserted and PWRGOOD deasserted, PWRGOOD is serviced, and the PWRGOOD reset event disables the

PRGRESET function.

Unlike most other registers, the bits in this register (RESCFG) are only returned to their reset value by a PWRGOOD

reset. They are not cleared by any other kind of reset.

The AMDebug technology trace information is preserved only if a soft reset is generated to the CPU.

See the

Élan™SC520 Microcontroller User’s Manual, order #22004, for details about reset generation. Table 3-3

on page 3-6 provides a summary of ÉlanSC520 microcontroller reset sources and effects.

SYS_RST

Software System Reset

Software can write to this bit to trigger a one-shot system reset. The last value written is what

is read.

0 = Do not cause a one-shot system reset event to be generated.

1 = Cause a one-shot system reset event to be generated.

Setting the SYS_RST bit also causes GP bus and PCI-Bus resets to be generated.

If the PRG_RST_ENB bit is 1, setting the SYS_RST bit results in a system reset in which the

SDRAM configuration is maintained.

Bit

Name

Function

ELANSC520 Datasheet(PDF) 46 Page - Advanced Micro Devices