ELANSC520 datasheet(84/440 Pages) AMD

84 / 440 page

PCI Bus Host Bridge Registers

6-20

Élan™SC520 Microcontroller Register Set Manual

R_MST_ABT

Received Master Abort

This bit is set by the host bridge master controller when its transaction is terminated with a

master abort.

0 = Transaction was not terminated with a master abort.

1 = Transaction was terminated with a master abort.

This bit is cleared by writing a 1.

R_TGT_ABT

Received Target Abort

This bit is set by the host bridge master controller when its transaction is terminated with a

target abort.

0 = Transaction was not terminated with a target abort.

1 = Transaction was terminated with a target abort.

This bit is cleared by writing a 1.

S_TGT_ABT

Signaled Target Abort

This bit is set by the host bridge target controller when it terminates a transaction with a target

abort. The host bridge responds with a target abort when an address parity error is detected.

0 = Target controller did not end a transaction with a target abort.

1 = Target controller ended a transaction with a target abort.

This bit is cleared by writing a 1.

–25

S_DVSL_TIM

–0]

Device Select (DEVSEL) Timing

These read only bits define the slowest DEVSEL timing for the host bridge target controller.

01 = The host bridge target controller always uses medium DEVSEL timing.

This bit field is internally fixed to 01b.

D_PERR_DET

Data Parity Reported

This bit is set by the host bridge master controller when, during a host bridge master controller

PCI bus cycle, PERR is asserted by the host bridge or a PCI bus target, and the Parity Error

Response bit (PERR_RES in the PCISTACMD register, see page 6-21) is also set.

0 = The master controller did not detect parity error.

1 = The master controller detect parity error.

This bit is cleared by writing a 1.

FBTB

Fast Back-to-Back Capable

This read-only bit indicates the host bridge target controller is capable of fast back-to-back

transactions.

1 = The host bridge target controller is capable of fast back-to-back transactions.

UDFS

UDF Supported

This read-only bit indicates the host bridge does not support user-definable features.

0 = The host bridge does not support user-definable features.

66M_CAP

66 MHz Capable

This-read only bit indicates the host bridge is not 66-MHz capable.

0 = The host bridge is not 66-MHz capable.

–9

Reserved

This bit field should be written to 0 for normal system operation.

SERR_ENB

SERR Enable

This bit is normally used to enable the PCI bus agent to drive the SERR pin, however the host

bridge does not drive the SERR pin because all interrupt control is integrated within the

ÉlanSC520 microcontroller.

0 = The SERR pin is not driven by the ÉlanSC520 microcontroller.

This bit is internally fixed to 0.

Reserved

This bit field should be written to 0 for normal system operation.

Bit

Name

Function

ELANSC520 Datasheet(PDF) 84 Page - Advanced Micro Devices

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