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ELANSC520 Datasheet(PDF) 73 Page - Advanced Micro Devices |
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ELANSC520 Datasheet(HTML) 73 Page - Advanced Micro Devices |
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73 / 440 page  PCI Bus Host Bridge Registers Élan™SC520 Microcontroller Register Set Manual 6-9 Host Bridge Master Interrupt Control (HBMSTIRQCTL) Memory-Mapped MMCR Offset 66h Register Description This register contains bit fields for configuring and enabling host bridge master interrupts. Bit Definitions 15 14 13 12 11 10 9 8 Bit Reserved M_RTRTO_ IRQ_SEL M_TABRT_ IRQ_SEL M_MABRT_ IRQ_SEL M_SERR_ IRQ_SEL M_RPER_ IRQ_SEL M_DPER_ IRQ_SEL Reset 00000000 R/W RSV R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Reserved M_RTRTO_ IRQ_ENB M_TABRT_ IRQ_ENB M_MABRT_ IRQ_ENB M_SERR_ IRQ_ENB M_RPER_ IRQ_ENB M_DPER_ IRQ_ENB Reset 00000000 R/W RSV R/W R/W R/W R/W R/W R/W Bit Name Function 15 –14 Reserved Reserved This bit field should be written to 0 for normal system operation. 13 M_RTRTO_ IRQ_SEL Master Retry Time-Out Interrupt Select This bit allows master retry time-outs to generate an NMI instead of a maskable interrupt. 0 = Master retry time-outs generate a maskable interrupt. 1 = Master retry time-outs generate an NMI. 12 M_TABRT_ IRQ_SEL Master Target Abort Interrupt Select This bit allows master controller transactions that are terminated with a target abort to generate an NMI instead of a maskable interrupt. 0 = Master transactions that are terminated with a master abort generate a maskable interrupt. 1 = Master transactions that are terminated with a master abort generate an NMI. 11 M_MABRT_ IRQ_SEL Master Abort Interrupt Select This bit allows master controller transactions that are terminated with a master abort to generate an NMI instead of a maskable interrupt. 0 = Master transactions that are terminated with a master abort generate a maskable interrupt. 1 = Master transactions that are terminated with a master abort generate an NMI. 10 M_SERR_ IRQ_SEL Master System Error Interrupt Select This bit allows the assertion of the system error signal (SERR) to generate an NMI instead of a maskable interrupt. 0 = Assertion of the system error signal generates a maskable interrupt. 1 = Assertion of the system error signal generates an NMI. |
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