ELANSC520 datasheet(67/440 Pages) AMD

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PCI Bus Host Bridge Registers

Élan™SC520 Microcontroller Register Set Manual

6-3

Host Bridge Control (HBCTL)

Memory-Mapped

MMCR Offset 60h

This register contains bit fields for configuring the host bridge controller.

Bit Definitions

Bit

PCI_RST

Reserved

T_PURGE_

RD_ENB

T_DLYTR_ENB[1–0]

Reset

00000000

R/W

R/W!

RSV

R/W

Bit

Reserved

WPOST_

ENB

Reserved

Reset

00000000

R/W

RSV

R/W

RSV

Bit

Name

Function

PCI_RST

PCI Bus Reset

This bit controls the PCI bus RST signal pin. Reading this bit returns the value that was

written to it.

0 = Deassert the PCI bus reset signal.

1 = Assert the PCI bus reset signal.

Note that a PCI bus reset affects the host bridge-specific registers in the PCI configuration

space. See the PCI-indexed register descriptions beginning on page 6-18.

The PCI_RST bit must be cleared only in accordance with the PCI bus specification.

–11

Reserved

This bit field should be written to 0 for normal system operation.

T_PURGE_

RD_ENB

Target FIFO Purge Enable

This bit is provided for data coherency. It forces the host bridge target controller to snoop the

target read FIFOs when a PCI bus write transaction occurs.

0 = The target read FIFOs are not snooped during write transactions.

1 = The target read FIFOs are snooped during PCI bus write transactions. The target

controller purges any data in the read FIFOs when the write transaction falls within the

same cache line for a read or read-line command, or within the same 64 doublewords for a

read-multiple command.

The T_PURGE_RD_ENB bit must not be changed except during PCI bus initialization after a

system reset. See the

Élan™SC520 Microcontroller User’s Manual, order #22004, for

information about PCI bus initialization.

ELANSC520 Datasheet(PDF) 67 Page - Advanced Micro Devices

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