ELANSC520 datasheet(49/440 Pages) AMD

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Reset Generation Registers

Élan™SC520 Microcontroller Register Set Manual

3-7

SCP Data Port (SCPDATA)

Direct-Mapped

I/O Address 0060h

This register is used to emulate system control processor (SCP) a20 gate control.

Bit Definitions

Programming Notes

There is no internal storage element associated with this address. All accesses to this address go to the GP bus.

Additionally, writes to this address are snooped by the ÉlanSC520 microcontroller.

Bit

SCP_DATA

Reserved

A20_GATE

CPU_RST

Reset

00000010

R/W

Bit

Name

Function

–0

SCP_DATA

System Control Processor Data

All reads and writes to this port are echoed to the GP bus.

A20_GATE

A20 Gate Data

The ÉlanSC520 microcontroller has no external input pin for the a20 gate signal that would

normally be driven by an external PC/AT-compatible system control processor (SCP). In order

to maintain software compatibility, internal logic is provided to watch the GP bus for SCP a20

gate pin control command sequences.

Following a write of D1h to the SCPCMD register (see page 3-8), a write to this bit

(A20_GATE) has the following effect:

0 = Internal a20 propagation is disabled (address space wraps at 1 Mbyte).

1 = Internal a20 propagation is enabled (addresses above 1 Mbyte can be accessed).

This bit (A20_GATE) provides one of two sources of a20 gate control. The other source is the

A20G_CTL bit in the SYSCTLA register (see page 3-9). A logical OR of these two sources is

used to drive the Am5x86 CPU a20m signal. Therefore, a20 propagates if either source

enables a20 to propagate.

Note that this bit (A20_GATE) defaults to enabling a20 propagation.

CPU_RST

CPU Reset Control

On the ÉlanSC520 microcontroller, writing to this bit has no effect.

On a PC/AT-compatible system, setting this bit to 1 after a write of D1h to the SCP Command

Port (SCPCMD) register would hold the system in reset indefinitely.

ELANSC520 Datasheet(PDF) 49 Page - Advanced Micro Devices

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