ELANSC520 datasheet(45/440 Pages) AMD

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Reset Generation Registers

Élan™SC520 Microcontroller Register Set Manual

3-3

Reset Configuration (RESCFG)

Memory-Mapped

MMCR Offset D72h

This register provides a direct read/write port to program system reset and GP bus reset. It also provides a control

bit to enable or disable the programmable system reset function of the PRGRESET pin and another control bit to

enable the AMDebug™ technology.

Bit Definitions

Bit

Reserved

ICE_ON_

RST

PRG_RST_

ENB

GP_RST

SYS_RST

Reset

00000000

R/W

RSV

R/W!

R/W

R/W!

Bit

Name

Function

–4

Reserved

This bit field should be written to 0 for normal system operation.

ICE_ON_RST

Enter AMDebug™ Technology Mode on Next Reset

Setting this bit enables the microprocessor to enter AMDebug technology mode after a hard

or soft reset has been asserted to the Am5x86 CPU. Writes to this bit are ignored if the

AMDebug technology mode is not active. (The AMDebug technology mode is controlled by

the software that drives the AMDebug technology port.)

0 = Do not enter AMDebug technology mode on a CPU hard or soft reset.

1 = Enable the microprocessor to enter AMDebug technology mode on a CPU hard or soft

reset.

PRG_RST_

ENB

Programmable Reset Enable

0 = Programmable reset is disabled.

1 = Programmable reset is enabled.

Setting this bit enables programmable resets, during which SDRAM configuration and

SDRAM contents are preserved. After this bit is set, programmable resets can be generated

by one of four sources:

PRGRESET pin

Watchdog timer time-out-generated reset

Software write to the SYS_RST bit (with the PRG_RST_ENB bit set in the same write)

AMDebug technology system reset

If this bit (PRG_RST_ENB) is cleared, the PRGRESET pin has no function. The other

programmable reset sources, if generated, initiate non-SDRAM-preserving system resets.

This bit is cleared by default, so a toggle on the PRGRESET pin does not affect the

ÉlanSC520 microcontroller.

GP_RST

Software GP Bus Reset

Software can write to this bit to control the GPRESET pin and read back the pin’s state. The

internal registers are not affected.

0 = Deassert GP bus reset.

1 = Assert GP bus reset.

ELANSC520 Datasheet(PDF) 45 Page - Advanced Micro Devices

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