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Am5x86

® CPU Registers

Élan™SC520 Microcontroller Register Set Manual

4-3

Am5x86® CPU Control (CPUCTL)

Memory-Mapped

MMCR Offset 02h

This register controls the Am5x86 CPU’s cache write-back mode and clock speed.

Bit Definitions

Programming Notes

The Am5x86 CPU core is reset during a hard reset, and the Am5x86 CPU core clock frequency defaults to 100 MHz.

The Am5x86 CPU core clock frequency remains the same and the cache state and policy are unaffected by a soft

reset.

See the

Élan™SC520 Microcontroller User’s Manual, order #22004, for details about hard and soft resets.

Table 3-3 on page 3-6 provides a summary of ÉlanSC520 microcontroller reset sources and effects.

Bit

Reserved

CACHE_

WR_MODE

Reserved

CPU_CLK_SPD[1–0]

Reset

00000001

R/W

RSV

R/W

RSV

R/W

Bit

Name

Function

–5

Reserved

This bit field should be written to 0 for normal system operation.

CACHE_WR_

MODE

Cache Write Mode

This bit enables the write-back mode of the Am5x86 CPU cache.

0 = Write-back mode (default).

1 =Write-through mode. If this bit is set, the cache operates in write-through mode regardless

of the setting of the NW bit in the processor’s internal CR0 register, or the PWT bit of the

corresponding page table entry.

–2

Reserved

This bit field should be written to 0 for normal system operation.

–0

CPU_CLK_SPD

[1–0]

CPU Clock Speed

This bit field specifies the clock speed at which the Am5x86 CPU runs. Note that there is a

1 ms delay for the Am5x86 CPU PLL to switch to the new frequency after this bit field is

changed.

00 = Reserved

01 = 100 MHz (default)

10 = 133 MHz

11 = Reserved

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