ELANSC520 datasheet(58/440 Pages) AMD

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System Arbitration Registers

5-2

Élan™SC520 Microcontroller Register Set Manual

System Arbiter Control (SYSARBCTL)

Memory-Mapped

MMCR Offset 70h

This register contains control bits for the CPU bus arbiter and the PCI bus arbiter.

Bit Definitions

Programming Notes

Bit

Reserved

BUS_

PARK_SEL

CNCR_

MODE_

ENB

GNT_TO_

INT_ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

7–3

Reserved

This bit field should be written to 0 for normal system operation.

BUS_PARK_

SEL

PCI Bus Arbiter Bus Park

This bit controls which PCI master the PCI bus arbiter parks on when the PCI bus is idle.

0 = Park the PCI bus on the Am5x86 CPU.

1 = Park the PCI bus on the last PCI master that acquired the bus.

This bit must be 0 when operating in nonconcurrent mode.

The BUS_PARK_SEL bit must not be changed except when the PCI bus is currently parked on

the Am5x86 CPU. This is the default state after a system reset. See the Élan™SC520

Microcontroller User’s Manual, order #22004, for information about system arbiter initialization.

CNCR_MODE_

ENB

System Arbiter Concurrent Mode Enable

This bit enables the system arbiter to operate in concurrent mode. When operating in

nonconcurrent mode, the BUS_PARK_SEL bit must be configured to park on the Am5x86

CPU.

0 = The system arbiter operates in nonconcurrent mode.

1 = The system arbiter operates in concurrent mode.

The CNCR_MODE_ENB bit must not be changed except during system arbiter initialization

after a system reset. See the

Élan™SC520 Microcontroller User’s Manual, order #22004, for

information about system arbiter initialization.

GNT_TO_INT_

ENB

PCI Bus Arbiter Grant Time-Out Interrupt Enable

This bit is used to enable interrupts that are generated when the PCI bus arbiter detects a

grant time-out.

0 = Disable PCI bus arbiter interrupts.

1 = Enable PCI bus arbiter interrupts.

Note that the GNT_TO_STA bit of the PCIARBSTA register (see page 5-3) is set on PCI bus

arbiter grant time-outs regardless of the GNT_TO_INT_ENB bit value.

This interrupt source shares the interrupt controller input used by any host bridge interrupts

enabled in the HBTGTIRQCTL and HBMSTIRQCTL registers (see page 6-5 and page 6-9).

Before the GNT_TO_INT_ENB bit is set, the PCIHOSTMAP register (see page 12-17) must

be configured to route the interrupt to the appropriate interrupt request level and priority.

ELANSC520 Datasheet(PDF) 58 Page - Advanced Micro Devices

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