ELANSC520 datasheet(93/440 Pages) AMD

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SDRAM Controller Registers

Élan™SC520 Microcontroller Register Set Manual

7-5

SDRAM Bank Configuration (DRCCFG)

Memory-Mapped

MMCR Offset 14h

This register controls the address column width configuration and SDRAM internal bank count for devices installed

in each bank.

Note: A programmable reset preserves this register’s state.See the PRG_RST_ENB bit description on page 3-3.

Bit Definitions

Bit

BNK3_

BNK_CNT

Reserved

BNK3_COLWDTH[1–0]

BNK2_

BNK_CNT

Reserved

BNK2_COLWDTH[1–0]

Reset

00000000

R/W

RSV

R/W

RSV

R/W

Bit

BNK1_

BNK_CNT

Reserved

BNK1_COLWDTH[1–0]

BNK0_

BNK_CNT

Reserved

BNK0_COLWDTH[1–0]

Reset

00000000

R/W

RSV

R/W

RSV

R/W

Bit

Name

Function

BNK3_BNK_

CNT

Bank 3 Internal SDRAM Bank Count

This bit specifies the number of internal banks supported by the SDRAM devices.

0 = 2-bank device

1 = 4-bank device

Reserved

This bit field should be written to 0 for normal system operation.

–12

BNK3_

COLWDTH[1–0]

Bank 3 Column Address Width

These two bits specify the column address width of the SDRAM devices populated in Bank 3.

00 = 8-bit column address

01 = 9-bit column address

10 = 10-bit column address

11 = 11-bit column address

BNK2_BNK_

CNT

Bank 2 Internal SDRAM Bank Count

This bit specifies the number of internal banks supported by the SDRAM devices.

0 = 2-bank device

1 = 4-bank device

Reserved

This bit field should be written to 0 for normal system operation.

–8

BNK2_

COLWDTH[1–0]

Bank 2 Column Address Width

These two bits specify the column address width of the SDRAM devices populated in Bank 2.

00 = 8-bit column address

01 = 9-bit column address

10 = 10-bit column address

11 = 11-bit column address

ELANSC520 Datasheet(PDF) 93 Page - Advanced Micro Devices

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